1 /*
2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <errno.h>
11
12 #include <bl31/bl31.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_tables_v2.h>
18 #include <plat/common/platform.h>
19 #include <plat_arm.h>
20 #include <plat_console.h>
21
22 #include <custom_svc.h>
23 #include <plat_clkfunc.h>
24 #include <plat_fdt.h>
25 #include <plat_private.h>
26 #include <plat_startup.h>
27 #include "pm_api_sys.h"
28 #include "pm_client.h"
29 #include <pm_ipi.h>
30 #include <versal_def.h>
31
32 static entry_point_info_t bl32_image_ep_info;
33 static entry_point_info_t bl33_image_ep_info;
34
35 /*
36 * Return a pointer to the 'entry_point_info' structure of the next image for
37 * the security state specified. BL33 corresponds to the non-secure image type
38 * while BL32 corresponds to the secure image type. A NULL pointer is returned
39 * if the image does not exist.
40 */
bl31_plat_get_next_image_ep_info(uint32_t type)41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
42 {
43 assert(sec_state_is_valid(type));
44
45 if (type == NON_SECURE) {
46 return &bl33_image_ep_info;
47 }
48
49 return &bl32_image_ep_info;
50 }
51
52 /*
53 * Set the build time defaults,if we can't find any config data.
54 */
bl31_set_default_config(void)55 static inline void bl31_set_default_config(void)
56 {
57 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
58 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr(BL32_IMAGE_ID);
59 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
60 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
61 DISABLE_ALL_EXCEPTIONS);
62 }
63
64 /*
65 * Perform any BL31 specific platform actions. Here is an opportunity to copy
66 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
67 * are lost (potentially). This needs to be done before the MMU is initialized
68 * so that the memory layout can be used while creating page tables.
69 */
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
71 u_register_t arg2, u_register_t arg3)
72 {
73 (void)arg0;
74 (void)arg1;
75 (void)arg2;
76 (void)arg3;
77 uint64_t tfa_handoff_addr;
78 uint32_t payload[PAYLOAD_ARG_CNT], max_size = (uint32_t)HANDOFF_PARAMS_MAX_SIZE;
79 enum pm_ret_status ret_status;
80 const uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
81
82 /*
83 * Do initial security configuration to allow DRAM/device access. On
84 * Base VERSAL only DRAM security is programmable (via TrustZone), but
85 * other platforms might have more programmable security devices
86 * present.
87 */
88 versal_config_setup();
89
90 /* Initialize the platform config for future decision making */
91 board_detection();
92
93 switch (platform_id) {
94 case VERSAL_SPP:
95 cpu_clock = 2720000;
96 break;
97 case VERSAL_EMU:
98 cpu_clock = 212000;
99 break;
100 case VERSAL_QEMU:
101 case VERSAL_SILICON:
102 cpu_clock = 100000000;
103 break;
104 default:
105 panic();
106 }
107 set_cnt_freq();
108
109 generic_delay_timer_init();
110
111 setup_console();
112
113 NOTICE("TF-A running on %s %d\n", board_name_decode(), platform_version);
114
115 /* Populate common information for BL32 and BL33 */
116 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
117 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
118 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
119 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
120
121 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS,
122 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
123 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
124 if (ret_status == PM_RET_SUCCESS) {
125 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
126 tfa_handoff_addr = (uintptr_t)&addr;
127 } else {
128 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n");
129 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
130 }
131
132 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info,
133 &bl33_image_ep_info,
134 tfa_handoff_addr);
135 if ((ret == XBL_HANDOFF_NO_STRUCT) || (ret == XBL_HANDOFF_INVAL_STRUCT)) {
136 bl31_set_default_config();
137 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) {
138 ERROR("BL31: Error too many partitions %u\n", ret);
139 } else if (ret != XBL_HANDOFF_SUCCESS) {
140 panic();
141 } else {
142 INFO("BL31: PLM to TF-A handover success %u\n", ret);
143 }
144
145 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
146 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
147
148 custom_early_setup();
149 }
150
151 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
152
request_intr_type_el3(uint32_t id,interrupt_type_handler_t handler)153 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
154 {
155 static uint32_t index;
156 uint32_t i;
157 int ret = 0;
158
159 /* Validate 'handler' and 'id' parameters */
160 if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
161 ret = -EINVAL;
162 goto exit_label;
163 }
164
165 /* Check if a handler has already been registered */
166 for (i = 0; i < index; i++) {
167 if (id == type_el3_interrupt_table[i].id) {
168 ret = -EALREADY;
169 goto exit_label;
170 }
171 }
172
173 type_el3_interrupt_table[index].id = id;
174 type_el3_interrupt_table[index].handler = handler;
175
176 index++;
177
178 exit_label:
179 return ret;
180 }
181
rdo_el3_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)182 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
183 void *handle, void *cookie)
184 {
185 (void)id;
186 uint32_t intr_id;
187 uint32_t i;
188 uint64_t ret = 0;
189 interrupt_type_handler_t handler = NULL;
190
191 intr_id = plat_ic_get_pending_interrupt_id();
192
193 for (i = 0; i < MAX_INTR_EL3; i++) {
194 if (intr_id == type_el3_interrupt_table[i].id) {
195 handler = type_el3_interrupt_table[i].handler;
196 }
197 }
198
199 if (handler != NULL) {
200 ret = handler(intr_id, flags, handle, cookie);
201 }
202
203 return ret;
204 }
205
bl31_platform_setup(void)206 void bl31_platform_setup(void)
207 {
208 prepare_dtb();
209
210 /* Initialize the gic cpu and distributor interfaces */
211 plat_versal_gic_driver_init();
212 plat_versal_gic_init();
213 }
214
bl31_plat_runtime_setup(void)215 void bl31_plat_runtime_setup(void)
216 {
217 uint32_t flags = 0;
218 int32_t rc;
219
220 set_interrupt_rm_flag(flags, NON_SECURE);
221 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
222 rdo_el3_interrupt_handler, flags);
223 if (rc != 0) {
224 panic();
225 }
226
227 custom_runtime_setup();
228 }
229
230 /*
231 * Perform the very early platform specific architectural setup here.
232 */
bl31_plat_arch_setup(void)233 void bl31_plat_arch_setup(void)
234 {
235 plat_arm_interconnect_init();
236 plat_arm_interconnect_enter_coherency();
237
238 const mmap_region_t bl_regions[] = {
239 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \
240 (!defined(PLAT_XLAT_TABLES_DYNAMIC)))
241 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
242 MT_MEMORY | MT_RW | MT_NS),
243 #endif
244 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
245 MT_MEMORY | MT_RW | MT_SECURE),
246 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
247 MT_CODE | MT_SECURE),
248 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
249 MT_RO_DATA | MT_SECURE),
250 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
251 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
252 MT_DEVICE | MT_RW | MT_SECURE),
253 {0}
254 };
255
256 custom_mmap_add();
257
258 setup_page_tables(bl_regions, plat_get_mmap());
259 enable_mmu(0);
260 }
261