1 /* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 #include <plat_clkfunc.h> 21 22 #include <plat_fdt.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include "pm_api_sys.h" 26 #include "pm_client.h" 27 #include <pm_ipi.h> 28 #include <versal_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 56 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 uint64_t tfa_handoff_addr; 72 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 73 enum pm_ret_status ret_status; 74 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; 75 76 set_cnt_freq(); 77 78 setup_console(); 79 80 /* Initialize the platform config for future decision making */ 81 versal_config_setup(); 82 83 /* Get platform related information */ 84 board_detection(); 85 86 /* 87 * Do initial security configuration to allow DRAM/device access. On 88 * Base VERSAL only DRAM security is programmable (via TrustZone), but 89 * other platforms might have more programmable security devices 90 * present. 91 */ 92 93 /* Populate common information for BL32 and BL33 */ 94 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 96 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 97 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 98 99 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 100 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 101 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 102 if (ret_status == PM_RET_SUCCESS) { 103 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 104 tfa_handoff_addr = (uintptr_t)&addr; 105 } else { 106 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n"); 107 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 108 } 109 110 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 111 &bl33_image_ep_info, 112 tfa_handoff_addr); 113 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) { 114 bl31_set_default_config(); 115 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) { 116 ERROR("BL31: Error too many partitions %u\n", ret); 117 } else if (ret != XBL_HANDOFF_SUCCESS) { 118 panic(); 119 } else { 120 INFO("BL31: PLM to TF-A handover success %u\n", ret); 121 } 122 123 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 124 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 125 } 126 127 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 128 129 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 130 { 131 static uint32_t index; 132 uint32_t i; 133 134 /* Validate 'handler' and 'id' parameters */ 135 if (handler == NULL || index >= MAX_INTR_EL3) { 136 return -EINVAL; 137 } 138 139 /* Check if a handler has already been registered */ 140 for (i = 0; i < index; i++) { 141 if (id == type_el3_interrupt_table[i].id) { 142 return -EALREADY; 143 } 144 } 145 146 type_el3_interrupt_table[index].id = id; 147 type_el3_interrupt_table[index].handler = handler; 148 149 index++; 150 151 return 0; 152 } 153 154 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 155 void *handle, void *cookie) 156 { 157 uint32_t intr_id; 158 uint32_t i; 159 interrupt_type_handler_t handler = NULL; 160 161 intr_id = plat_ic_get_pending_interrupt_id(); 162 163 for (i = 0; i < MAX_INTR_EL3; i++) { 164 if (intr_id == type_el3_interrupt_table[i].id) { 165 handler = type_el3_interrupt_table[i].handler; 166 } 167 } 168 169 if (handler != NULL) { 170 return handler(intr_id, flags, handle, cookie); 171 } 172 173 return 0; 174 } 175 176 void bl31_platform_setup(void) 177 { 178 prepare_dtb(); 179 180 /* Initialize the gic cpu and distributor interfaces */ 181 plat_versal_gic_driver_init(); 182 plat_versal_gic_init(); 183 } 184 185 void bl31_plat_runtime_setup(void) 186 { 187 uint64_t flags = 0; 188 int32_t rc; 189 190 set_interrupt_rm_flag(flags, NON_SECURE); 191 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 192 rdo_el3_interrupt_handler, flags); 193 if (rc != 0) { 194 panic(); 195 } 196 } 197 198 /* 199 * Perform the very early platform specific architectural setup here. 200 */ 201 void bl31_plat_arch_setup(void) 202 { 203 plat_arm_interconnect_init(); 204 plat_arm_interconnect_enter_coherency(); 205 206 const mmap_region_t bl_regions[] = { 207 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \ 208 (!defined(PLAT_XLAT_TABLES_DYNAMIC))) 209 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 210 MT_MEMORY | MT_RW | MT_NS), 211 #endif 212 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 213 MT_MEMORY | MT_RW | MT_SECURE), 214 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 215 MT_CODE | MT_SECURE), 216 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 217 MT_RO_DATA | MT_SECURE), 218 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 219 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 220 MT_DEVICE | MT_RW | MT_SECURE), 221 {0} 222 }; 223 224 setup_page_tables(bl_regions, plat_get_mmap()); 225 enable_mmu(0); 226 } 227