1 /* 2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <plat_arm.h> 10 #include <plat_private.h> 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/dcc.h> 15 #include <drivers/arm/pl011.h> 16 #include <drivers/console.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables.h> 19 #include <plat/common/platform.h> 20 #include <versal_def.h> 21 #include <plat_private.h> 22 #include <plat_startup.h> 23 #include <pm_ipi.h> 24 #include "pm_client.h" 25 #include "pm_api_sys.h" 26 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 30 /* 31 * Return a pointer to the 'entry_point_info' structure of the next image for 32 * the security state specified. BL33 corresponds to the non-secure image type 33 * while BL32 corresponds to the secure image type. A NULL pointer is returned 34 * if the image does not exist. 35 */ 36 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 37 { 38 assert(sec_state_is_valid(type)); 39 40 if (type == NON_SECURE) { 41 return &bl33_image_ep_info; 42 } 43 44 return &bl32_image_ep_info; 45 } 46 47 /* 48 * Set the build time defaults,if we can't find any config data. 49 */ 50 static inline void bl31_set_default_config(void) 51 { 52 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 53 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 54 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 55 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 56 DISABLE_ALL_EXCEPTIONS); 57 } 58 59 /* 60 * Perform any BL31 specific platform actions. Here is an opportunity to copy 61 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 62 * are lost (potentially). This needs to be done before the MMU is initialized 63 * so that the memory layout can be used while creating page tables. 64 */ 65 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 66 u_register_t arg2, u_register_t arg3) 67 { 68 uint64_t atf_handoff_addr; 69 uint32_t payload[PAYLOAD_ARG_CNT], max_size = ATF_HANDOFF_PARAMS_MAX_SIZE; 70 enum pm_ret_status ret_status; 71 uint64_t addr[ATF_HANDOFF_PARAMS_MAX_SIZE]; 72 73 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { 74 static console_t versal_runtime_console; 75 /* Initialize the console to provide early debug support */ 76 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE, 77 (uint32_t)VERSAL_UART_CLOCK, 78 (uint32_t)VERSAL_UART_BAUDRATE, 79 &versal_runtime_console); 80 if (rc == 0) { 81 panic(); 82 } 83 84 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT | 85 CONSOLE_FLAG_RUNTIME)); 86 } else if (VERSAL_CONSOLE_IS(dcc)) { 87 /* Initialize the dcc console for debug */ 88 int32_t rc = console_dcc_register(); 89 if (rc == 0) { 90 panic(); 91 } 92 } else { 93 NOTICE("BL31: Did not register for any console.\n"); 94 } 95 96 /* Initialize the platform config for future decision making */ 97 versal_config_setup(); 98 /* There are no parameters from BL2 if BL31 is a reset vector */ 99 assert(arg0 == 0U); 100 assert(arg1 == 0U); 101 102 /* 103 * Do initial security configuration to allow DRAM/device access. On 104 * Base VERSAL only DRAM security is programmable (via TrustZone), but 105 * other platforms might have more programmable security devices 106 * present. 107 */ 108 109 /* Populate common information for BL32 and BL33 */ 110 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 111 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 112 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 113 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 114 115 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 116 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 117 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 118 if (ret_status == PM_RET_SUCCESS) { 119 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 120 atf_handoff_addr = (uintptr_t)&addr; 121 } else { 122 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read atf_handoff_addr from reg\n"); 123 atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 124 } 125 126 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 127 &bl33_image_ep_info, 128 atf_handoff_addr); 129 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) { 130 bl31_set_default_config(); 131 } else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) { 132 ERROR("BL31: Error too many partitions %u\n", ret); 133 } else if (ret != FSBL_HANDOFF_SUCCESS) { 134 panic(); 135 } else { 136 INFO("BL31: fsbl-atf handover success %u\n", ret); 137 } 138 139 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 140 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 141 } 142 143 static interrupt_type_handler_t type_el3_interrupt_handler; 144 145 int32_t request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 146 { 147 /* Validate 'handler'*/ 148 if (handler == NULL) { 149 return -EINVAL; 150 } 151 152 type_el3_interrupt_handler = handler; 153 154 return 0; 155 } 156 157 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 158 void *handle, void *cookie) 159 { 160 uint32_t intr_id; 161 interrupt_type_handler_t handler; 162 163 intr_id = plat_ic_get_pending_interrupt_id(); 164 /* Currently we support one interrupt */ 165 if (intr_id != PLAT_VERSAL_IPI_IRQ) { 166 WARN("Unexpected interrupt call: 0x%x\n", intr_id); 167 return 0; 168 } 169 170 handler = type_el3_interrupt_handler; 171 if (handler != NULL) { 172 return handler(intr_id, flags, handle, cookie); 173 } 174 175 return 0; 176 } 177 void bl31_platform_setup(void) 178 { 179 /* Initialize the gic cpu and distributor interfaces */ 180 plat_versal_gic_driver_init(); 181 plat_versal_gic_init(); 182 } 183 184 void bl31_plat_runtime_setup(void) 185 { 186 uint64_t flags = 0; 187 int32_t rc; 188 189 set_interrupt_rm_flag(flags, NON_SECURE); 190 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 191 rdo_el3_interrupt_handler, flags); 192 if (rc != 0) { 193 panic(); 194 } 195 } 196 197 /* 198 * Perform the very early platform specific architectural setup here. 199 */ 200 void bl31_plat_arch_setup(void) 201 { 202 plat_arm_interconnect_init(); 203 plat_arm_interconnect_enter_coherency(); 204 205 const mmap_region_t bl_regions[] = { 206 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 207 MT_MEMORY | MT_RW | MT_SECURE), 208 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 209 MT_CODE | MT_SECURE), 210 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 211 MT_RO_DATA | MT_SECURE), 212 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 213 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 214 MT_DEVICE | MT_RW | MT_SECURE), 215 {0} 216 }; 217 218 setup_page_tables(bl_regions, plat_versal_get_mmap()); 219 enable_mmu_el3(0); 220 } 221