1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <plat_arm.h> 22 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include "pm_api_sys.h" 26 #include "pm_client.h" 27 #include <pm_ipi.h> 28 #include <versal_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 56 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 uint64_t tfa_handoff_addr; 72 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 73 enum pm_ret_status ret_status; 74 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; 75 76 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { 77 static console_t versal_runtime_console; 78 /* Initialize the console to provide early debug support */ 79 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE, 80 (uint32_t)VERSAL_UART_CLOCK, 81 (uint32_t)VERSAL_UART_BAUDRATE, 82 &versal_runtime_console); 83 if (rc == 0) { 84 panic(); 85 } 86 87 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT | 88 CONSOLE_FLAG_RUNTIME)); 89 } else if (VERSAL_CONSOLE_IS(dcc)) { 90 /* Initialize the dcc console for debug */ 91 int32_t rc = console_dcc_register(); 92 if (rc == 0) { 93 panic(); 94 } 95 } else { 96 NOTICE("BL31: Did not register for any console.\n"); 97 } 98 99 /* Initialize the platform config for future decision making */ 100 versal_config_setup(); 101 102 /* Get platform related information */ 103 board_detection(); 104 105 /* 106 * Do initial security configuration to allow DRAM/device access. On 107 * Base VERSAL only DRAM security is programmable (via TrustZone), but 108 * other platforms might have more programmable security devices 109 * present. 110 */ 111 112 /* Populate common information for BL32 and BL33 */ 113 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 114 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 115 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 116 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 117 118 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 119 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 120 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 121 if (ret_status == PM_RET_SUCCESS) { 122 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 123 tfa_handoff_addr = (uintptr_t)&addr; 124 } else { 125 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n"); 126 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 127 } 128 129 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 130 &bl33_image_ep_info, 131 tfa_handoff_addr); 132 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) { 133 bl31_set_default_config(); 134 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) { 135 ERROR("BL31: Error too many partitions %u\n", ret); 136 } else if (ret != XBL_HANDOFF_SUCCESS) { 137 panic(); 138 } else { 139 INFO("BL31: PLM to TF-A handover success %u\n", ret); 140 } 141 142 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 143 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 144 } 145 146 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 147 148 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 149 { 150 static uint32_t index; 151 uint32_t i; 152 153 /* Validate 'handler' and 'id' parameters */ 154 if (handler == NULL || index >= MAX_INTR_EL3) { 155 return -EINVAL; 156 } 157 158 /* Check if a handler has already been registered */ 159 for (i = 0; i < index; i++) { 160 if (id == type_el3_interrupt_table[i].id) { 161 return -EALREADY; 162 } 163 } 164 165 type_el3_interrupt_table[index].id = id; 166 type_el3_interrupt_table[index].handler = handler; 167 168 index++; 169 170 return 0; 171 } 172 173 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 174 void *handle, void *cookie) 175 { 176 uint32_t intr_id; 177 uint32_t i; 178 interrupt_type_handler_t handler = NULL; 179 180 intr_id = plat_ic_get_pending_interrupt_id(); 181 182 for (i = 0; i < MAX_INTR_EL3; i++) { 183 if (intr_id == type_el3_interrupt_table[i].id) { 184 handler = type_el3_interrupt_table[i].handler; 185 } 186 } 187 188 if (handler != NULL) { 189 return handler(intr_id, flags, handle, cookie); 190 } 191 192 return 0; 193 } 194 void bl31_platform_setup(void) 195 { 196 /* Initialize the gic cpu and distributor interfaces */ 197 plat_versal_gic_driver_init(); 198 plat_versal_gic_init(); 199 } 200 201 void bl31_plat_runtime_setup(void) 202 { 203 uint64_t flags = 0; 204 int32_t rc; 205 206 set_interrupt_rm_flag(flags, NON_SECURE); 207 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 208 rdo_el3_interrupt_handler, flags); 209 if (rc != 0) { 210 panic(); 211 } 212 } 213 214 /* 215 * Perform the very early platform specific architectural setup here. 216 */ 217 void bl31_plat_arch_setup(void) 218 { 219 plat_arm_interconnect_init(); 220 plat_arm_interconnect_enter_coherency(); 221 222 const mmap_region_t bl_regions[] = { 223 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 224 MT_MEMORY | MT_RW | MT_SECURE), 225 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 226 MT_CODE | MT_SECURE), 227 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 228 MT_RO_DATA | MT_SECURE), 229 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 230 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 231 MT_DEVICE | MT_RW | MT_SECURE), 232 {0} 233 }; 234 235 setup_page_tables(bl_regions, plat_versal_get_mmap()); 236 enable_mmu(0); 237 } 238