xref: /rk3399_ARM-atf/plat/xilinx/versal/bl31_versal_setup.c (revision f91c3cb1df7d41122185063453f39dfe90119b5b)
1*f91c3cb1SSiva Durga Prasad Paladugu /*
2*f91c3cb1SSiva Durga Prasad Paladugu  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*f91c3cb1SSiva Durga Prasad Paladugu  *
4*f91c3cb1SSiva Durga Prasad Paladugu  * SPDX-License-Identifier: BSD-3-Clause
5*f91c3cb1SSiva Durga Prasad Paladugu  */
6*f91c3cb1SSiva Durga Prasad Paladugu 
7*f91c3cb1SSiva Durga Prasad Paladugu #include <assert.h>
8*f91c3cb1SSiva Durga Prasad Paladugu #include <bl_common.h>
9*f91c3cb1SSiva Durga Prasad Paladugu #include <bl31.h>
10*f91c3cb1SSiva Durga Prasad Paladugu #include <console.h>
11*f91c3cb1SSiva Durga Prasad Paladugu #include <debug.h>
12*f91c3cb1SSiva Durga Prasad Paladugu #include <errno.h>
13*f91c3cb1SSiva Durga Prasad Paladugu #include <platform.h>
14*f91c3cb1SSiva Durga Prasad Paladugu #include <pl011.h>
15*f91c3cb1SSiva Durga Prasad Paladugu #include <xlat_tables.h>
16*f91c3cb1SSiva Durga Prasad Paladugu #include "versal_private.h"
17*f91c3cb1SSiva Durga Prasad Paladugu 
18*f91c3cb1SSiva Durga Prasad Paladugu static entry_point_info_t bl32_image_ep_info;
19*f91c3cb1SSiva Durga Prasad Paladugu static entry_point_info_t bl33_image_ep_info;
20*f91c3cb1SSiva Durga Prasad Paladugu static console_pl011_t versal_runtime_console;
21*f91c3cb1SSiva Durga Prasad Paladugu 
22*f91c3cb1SSiva Durga Prasad Paladugu /*
23*f91c3cb1SSiva Durga Prasad Paladugu  * Return a pointer to the 'entry_point_info' structure of the next image for
24*f91c3cb1SSiva Durga Prasad Paladugu  * the security state specified. BL33 corresponds to the non-secure image type
25*f91c3cb1SSiva Durga Prasad Paladugu  * while BL32 corresponds to the secure image type. A NULL pointer is returned
26*f91c3cb1SSiva Durga Prasad Paladugu  * if the image does not exist.
27*f91c3cb1SSiva Durga Prasad Paladugu  */
28*f91c3cb1SSiva Durga Prasad Paladugu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
29*f91c3cb1SSiva Durga Prasad Paladugu {
30*f91c3cb1SSiva Durga Prasad Paladugu 	assert(sec_state_is_valid(type));
31*f91c3cb1SSiva Durga Prasad Paladugu 
32*f91c3cb1SSiva Durga Prasad Paladugu 	if (type == NON_SECURE)
33*f91c3cb1SSiva Durga Prasad Paladugu 		return &bl33_image_ep_info;
34*f91c3cb1SSiva Durga Prasad Paladugu 
35*f91c3cb1SSiva Durga Prasad Paladugu 	return &bl32_image_ep_info;
36*f91c3cb1SSiva Durga Prasad Paladugu }
37*f91c3cb1SSiva Durga Prasad Paladugu 
38*f91c3cb1SSiva Durga Prasad Paladugu /*
39*f91c3cb1SSiva Durga Prasad Paladugu  * Perform any BL31 specific platform actions. Here is an opportunity to copy
40*f91c3cb1SSiva Durga Prasad Paladugu  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
41*f91c3cb1SSiva Durga Prasad Paladugu  * are lost (potentially). This needs to be done before the MMU is initialized
42*f91c3cb1SSiva Durga Prasad Paladugu  * so that the memory layout can be used while creating page tables.
43*f91c3cb1SSiva Durga Prasad Paladugu  */
44*f91c3cb1SSiva Durga Prasad Paladugu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
45*f91c3cb1SSiva Durga Prasad Paladugu 				u_register_t arg2, u_register_t arg3)
46*f91c3cb1SSiva Durga Prasad Paladugu {
47*f91c3cb1SSiva Durga Prasad Paladugu 
48*f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the console to provide early debug support */
49*f91c3cb1SSiva Durga Prasad Paladugu 	int rc = console_pl011_register(VERSAL_UART_BASE,
50*f91c3cb1SSiva Durga Prasad Paladugu 					VERSAL_UART_CLOCK,
51*f91c3cb1SSiva Durga Prasad Paladugu 					VERSAL_UART_BAUDRATE,
52*f91c3cb1SSiva Durga Prasad Paladugu 					&versal_runtime_console);
53*f91c3cb1SSiva Durga Prasad Paladugu 	if (rc == 0)
54*f91c3cb1SSiva Durga Prasad Paladugu 		panic();
55*f91c3cb1SSiva Durga Prasad Paladugu 
56*f91c3cb1SSiva Durga Prasad Paladugu 	console_set_scope(&versal_runtime_console.console, CONSOLE_FLAG_BOOT |
57*f91c3cb1SSiva Durga Prasad Paladugu 			  CONSOLE_FLAG_RUNTIME);
58*f91c3cb1SSiva Durga Prasad Paladugu 
59*f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the platform config for future decision making */
60*f91c3cb1SSiva Durga Prasad Paladugu 	versal_config_setup();
61*f91c3cb1SSiva Durga Prasad Paladugu 	/* There are no parameters from BL2 if BL31 is a reset vector */
62*f91c3cb1SSiva Durga Prasad Paladugu 	assert(arg0 == 0U);
63*f91c3cb1SSiva Durga Prasad Paladugu 	assert(arg1 == 0U);
64*f91c3cb1SSiva Durga Prasad Paladugu 
65*f91c3cb1SSiva Durga Prasad Paladugu 	/*
66*f91c3cb1SSiva Durga Prasad Paladugu 	 * Do initial security configuration to allow DRAM/device access. On
67*f91c3cb1SSiva Durga Prasad Paladugu 	 * Base VERSAL only DRAM security is programmable (via TrustZone), but
68*f91c3cb1SSiva Durga Prasad Paladugu 	 * other platforms might have more programmable security devices
69*f91c3cb1SSiva Durga Prasad Paladugu 	 * present.
70*f91c3cb1SSiva Durga Prasad Paladugu 	 */
71*f91c3cb1SSiva Durga Prasad Paladugu 
72*f91c3cb1SSiva Durga Prasad Paladugu 	/* Populate common information for BL32 and BL33 */
73*f91c3cb1SSiva Durga Prasad Paladugu 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
74*f91c3cb1SSiva Durga Prasad Paladugu 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
75*f91c3cb1SSiva Durga Prasad Paladugu 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
76*f91c3cb1SSiva Durga Prasad Paladugu 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
77*f91c3cb1SSiva Durga Prasad Paladugu 
78*f91c3cb1SSiva Durga Prasad Paladugu 	/* use build time defaults in JTAG boot mode */
79*f91c3cb1SSiva Durga Prasad Paladugu 	bl32_image_ep_info.pc = BL32_BASE;
80*f91c3cb1SSiva Durga Prasad Paladugu 	bl32_image_ep_info.spsr = 0;
81*f91c3cb1SSiva Durga Prasad Paladugu 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
82*f91c3cb1SSiva Durga Prasad Paladugu 	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
83*f91c3cb1SSiva Durga Prasad Paladugu 					  DISABLE_ALL_EXCEPTIONS);
84*f91c3cb1SSiva Durga Prasad Paladugu 
85*f91c3cb1SSiva Durga Prasad Paladugu 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
86*f91c3cb1SSiva Durga Prasad Paladugu 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
87*f91c3cb1SSiva Durga Prasad Paladugu }
88*f91c3cb1SSiva Durga Prasad Paladugu 
89*f91c3cb1SSiva Durga Prasad Paladugu void bl31_platform_setup(void)
90*f91c3cb1SSiva Durga Prasad Paladugu {
91*f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the gic cpu and distributor interfaces */
92*f91c3cb1SSiva Durga Prasad Paladugu 	plat_versal_gic_driver_init();
93*f91c3cb1SSiva Durga Prasad Paladugu 	plat_versal_gic_init();
94*f91c3cb1SSiva Durga Prasad Paladugu }
95*f91c3cb1SSiva Durga Prasad Paladugu 
96*f91c3cb1SSiva Durga Prasad Paladugu void bl31_plat_runtime_setup(void)
97*f91c3cb1SSiva Durga Prasad Paladugu {
98*f91c3cb1SSiva Durga Prasad Paladugu }
99*f91c3cb1SSiva Durga Prasad Paladugu 
100*f91c3cb1SSiva Durga Prasad Paladugu /*
101*f91c3cb1SSiva Durga Prasad Paladugu  * Perform the very early platform specific architectural setup here.
102*f91c3cb1SSiva Durga Prasad Paladugu  */
103*f91c3cb1SSiva Durga Prasad Paladugu void bl31_plat_arch_setup(void)
104*f91c3cb1SSiva Durga Prasad Paladugu {
105*f91c3cb1SSiva Durga Prasad Paladugu 	const mmap_region_t bl_regions[] = {
106*f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
107*f91c3cb1SSiva Durga Prasad Paladugu 			MT_MEMORY | MT_RW | MT_SECURE),
108*f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
109*f91c3cb1SSiva Durga Prasad Paladugu 				MT_CODE | MT_SECURE),
110*f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
111*f91c3cb1SSiva Durga Prasad Paladugu 				MT_RO_DATA | MT_SECURE),
112*f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
113*f91c3cb1SSiva Durga Prasad Paladugu 				BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
114*f91c3cb1SSiva Durga Prasad Paladugu 				MT_DEVICE | MT_RW | MT_SECURE),
115*f91c3cb1SSiva Durga Prasad Paladugu 		{0}
116*f91c3cb1SSiva Durga Prasad Paladugu 	};
117*f91c3cb1SSiva Durga Prasad Paladugu 
118*f91c3cb1SSiva Durga Prasad Paladugu 	setup_page_tables(bl_regions, plat_versal_get_mmap());
119*f91c3cb1SSiva Durga Prasad Paladugu 	enable_mmu_el3(0);
120*f91c3cb1SSiva Durga Prasad Paladugu }
121