xref: /rk3399_ARM-atf/plat/xilinx/versal/bl31_versal_setup.c (revision d4821739ef36f8fda5504fa5c57e0c41f0e09c24)
1f91c3cb1SSiva Durga Prasad Paladugu /*
2*d4821739STejas Patel  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3f91c3cb1SSiva Durga Prasad Paladugu  *
4f91c3cb1SSiva Durga Prasad Paladugu  * SPDX-License-Identifier: BSD-3-Clause
5f91c3cb1SSiva Durga Prasad Paladugu  */
6f91c3cb1SSiva Durga Prasad Paladugu 
7f91c3cb1SSiva Durga Prasad Paladugu #include <assert.h>
8f91c3cb1SSiva Durga Prasad Paladugu #include <errno.h>
9*d4821739STejas Patel #include <plat_private.h>
1009d40e0eSAntonio Nino Diaz #include <bl31/bl31.h>
1109d40e0eSAntonio Nino Diaz #include <common/bl_common.h>
1209d40e0eSAntonio Nino Diaz #include <common/debug.h>
1309d40e0eSAntonio Nino Diaz #include <drivers/arm/pl011.h>
1409d40e0eSAntonio Nino Diaz #include <drivers/console.h>
1509d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables.h>
1609d40e0eSAntonio Nino Diaz #include <plat/common/platform.h>
1709d40e0eSAntonio Nino Diaz 
18f91c3cb1SSiva Durga Prasad Paladugu static entry_point_info_t bl32_image_ep_info;
19f91c3cb1SSiva Durga Prasad Paladugu static entry_point_info_t bl33_image_ep_info;
20f91c3cb1SSiva Durga Prasad Paladugu static console_pl011_t versal_runtime_console;
21f91c3cb1SSiva Durga Prasad Paladugu 
22f91c3cb1SSiva Durga Prasad Paladugu /*
23f91c3cb1SSiva Durga Prasad Paladugu  * Return a pointer to the 'entry_point_info' structure of the next image for
24f91c3cb1SSiva Durga Prasad Paladugu  * the security state specified. BL33 corresponds to the non-secure image type
25f91c3cb1SSiva Durga Prasad Paladugu  * while BL32 corresponds to the secure image type. A NULL pointer is returned
26f91c3cb1SSiva Durga Prasad Paladugu  * if the image does not exist.
27f91c3cb1SSiva Durga Prasad Paladugu  */
28f91c3cb1SSiva Durga Prasad Paladugu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
29f91c3cb1SSiva Durga Prasad Paladugu {
30f91c3cb1SSiva Durga Prasad Paladugu 	assert(sec_state_is_valid(type));
31f91c3cb1SSiva Durga Prasad Paladugu 
32f91c3cb1SSiva Durga Prasad Paladugu 	if (type == NON_SECURE)
33f91c3cb1SSiva Durga Prasad Paladugu 		return &bl33_image_ep_info;
34f91c3cb1SSiva Durga Prasad Paladugu 
35f91c3cb1SSiva Durga Prasad Paladugu 	return &bl32_image_ep_info;
36f91c3cb1SSiva Durga Prasad Paladugu }
37f91c3cb1SSiva Durga Prasad Paladugu 
38f91c3cb1SSiva Durga Prasad Paladugu /*
39f91c3cb1SSiva Durga Prasad Paladugu  * Perform any BL31 specific platform actions. Here is an opportunity to copy
40f91c3cb1SSiva Durga Prasad Paladugu  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
41f91c3cb1SSiva Durga Prasad Paladugu  * are lost (potentially). This needs to be done before the MMU is initialized
42f91c3cb1SSiva Durga Prasad Paladugu  * so that the memory layout can be used while creating page tables.
43f91c3cb1SSiva Durga Prasad Paladugu  */
44f91c3cb1SSiva Durga Prasad Paladugu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
45f91c3cb1SSiva Durga Prasad Paladugu 				u_register_t arg2, u_register_t arg3)
46f91c3cb1SSiva Durga Prasad Paladugu {
47f91c3cb1SSiva Durga Prasad Paladugu 
48f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the console to provide early debug support */
49f91c3cb1SSiva Durga Prasad Paladugu 	int rc = console_pl011_register(VERSAL_UART_BASE,
50f91c3cb1SSiva Durga Prasad Paladugu 					VERSAL_UART_CLOCK,
51f91c3cb1SSiva Durga Prasad Paladugu 					VERSAL_UART_BAUDRATE,
52f91c3cb1SSiva Durga Prasad Paladugu 					&versal_runtime_console);
53f91c3cb1SSiva Durga Prasad Paladugu 	if (rc == 0)
54f91c3cb1SSiva Durga Prasad Paladugu 		panic();
55f91c3cb1SSiva Durga Prasad Paladugu 
56f91c3cb1SSiva Durga Prasad Paladugu 	console_set_scope(&versal_runtime_console.console, CONSOLE_FLAG_BOOT |
57f91c3cb1SSiva Durga Prasad Paladugu 			  CONSOLE_FLAG_RUNTIME);
58f91c3cb1SSiva Durga Prasad Paladugu 
59f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the platform config for future decision making */
60f91c3cb1SSiva Durga Prasad Paladugu 	versal_config_setup();
61f91c3cb1SSiva Durga Prasad Paladugu 	/* There are no parameters from BL2 if BL31 is a reset vector */
62f91c3cb1SSiva Durga Prasad Paladugu 	assert(arg0 == 0U);
63f91c3cb1SSiva Durga Prasad Paladugu 	assert(arg1 == 0U);
64f91c3cb1SSiva Durga Prasad Paladugu 
65f91c3cb1SSiva Durga Prasad Paladugu 	/*
66f91c3cb1SSiva Durga Prasad Paladugu 	 * Do initial security configuration to allow DRAM/device access. On
67f91c3cb1SSiva Durga Prasad Paladugu 	 * Base VERSAL only DRAM security is programmable (via TrustZone), but
68f91c3cb1SSiva Durga Prasad Paladugu 	 * other platforms might have more programmable security devices
69f91c3cb1SSiva Durga Prasad Paladugu 	 * present.
70f91c3cb1SSiva Durga Prasad Paladugu 	 */
71f91c3cb1SSiva Durga Prasad Paladugu 
72f91c3cb1SSiva Durga Prasad Paladugu 	/* Populate common information for BL32 and BL33 */
73f91c3cb1SSiva Durga Prasad Paladugu 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
74f91c3cb1SSiva Durga Prasad Paladugu 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
75f91c3cb1SSiva Durga Prasad Paladugu 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
76f91c3cb1SSiva Durga Prasad Paladugu 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
77f91c3cb1SSiva Durga Prasad Paladugu 
78f91c3cb1SSiva Durga Prasad Paladugu 	/* use build time defaults in JTAG boot mode */
79f91c3cb1SSiva Durga Prasad Paladugu 	bl32_image_ep_info.pc = BL32_BASE;
80f91c3cb1SSiva Durga Prasad Paladugu 	bl32_image_ep_info.spsr = 0;
81f91c3cb1SSiva Durga Prasad Paladugu 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
82f91c3cb1SSiva Durga Prasad Paladugu 	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
83f91c3cb1SSiva Durga Prasad Paladugu 					  DISABLE_ALL_EXCEPTIONS);
84f91c3cb1SSiva Durga Prasad Paladugu 
85f91c3cb1SSiva Durga Prasad Paladugu 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
86f91c3cb1SSiva Durga Prasad Paladugu 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
87f91c3cb1SSiva Durga Prasad Paladugu }
88f91c3cb1SSiva Durga Prasad Paladugu 
89f91c3cb1SSiva Durga Prasad Paladugu void bl31_platform_setup(void)
90f91c3cb1SSiva Durga Prasad Paladugu {
91f91c3cb1SSiva Durga Prasad Paladugu 	/* Initialize the gic cpu and distributor interfaces */
92f91c3cb1SSiva Durga Prasad Paladugu 	plat_versal_gic_driver_init();
93f91c3cb1SSiva Durga Prasad Paladugu 	plat_versal_gic_init();
94f91c3cb1SSiva Durga Prasad Paladugu }
95f91c3cb1SSiva Durga Prasad Paladugu 
96f91c3cb1SSiva Durga Prasad Paladugu void bl31_plat_runtime_setup(void)
97f91c3cb1SSiva Durga Prasad Paladugu {
98f91c3cb1SSiva Durga Prasad Paladugu }
99f91c3cb1SSiva Durga Prasad Paladugu 
100f91c3cb1SSiva Durga Prasad Paladugu /*
101f91c3cb1SSiva Durga Prasad Paladugu  * Perform the very early platform specific architectural setup here.
102f91c3cb1SSiva Durga Prasad Paladugu  */
103f91c3cb1SSiva Durga Prasad Paladugu void bl31_plat_arch_setup(void)
104f91c3cb1SSiva Durga Prasad Paladugu {
105f91c3cb1SSiva Durga Prasad Paladugu 	const mmap_region_t bl_regions[] = {
106f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
107f91c3cb1SSiva Durga Prasad Paladugu 			MT_MEMORY | MT_RW | MT_SECURE),
108f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
109f91c3cb1SSiva Durga Prasad Paladugu 				MT_CODE | MT_SECURE),
110f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
111f91c3cb1SSiva Durga Prasad Paladugu 				MT_RO_DATA | MT_SECURE),
112f91c3cb1SSiva Durga Prasad Paladugu 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
113f91c3cb1SSiva Durga Prasad Paladugu 				BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
114f91c3cb1SSiva Durga Prasad Paladugu 				MT_DEVICE | MT_RW | MT_SECURE),
115f91c3cb1SSiva Durga Prasad Paladugu 		{0}
116f91c3cb1SSiva Durga Prasad Paladugu 	};
117f91c3cb1SSiva Durga Prasad Paladugu 
118f91c3cb1SSiva Durga Prasad Paladugu 	setup_page_tables(bl_regions, plat_versal_get_mmap());
119f91c3cb1SSiva Durga Prasad Paladugu 	enable_mmu_el3(0);
120f91c3cb1SSiva Durga Prasad Paladugu }
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