1*f91c3cb1SSiva Durga Prasad Paladugu/* 2*f91c3cb1SSiva Durga Prasad Paladugu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*f91c3cb1SSiva Durga Prasad Paladugu * 4*f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause 5*f91c3cb1SSiva Durga Prasad Paladugu */ 6*f91c3cb1SSiva Durga Prasad Paladugu 7*f91c3cb1SSiva Durga Prasad Paladugu#include <arch.h> 8*f91c3cb1SSiva Durga Prasad Paladugu#include <asm_macros.S> 9*f91c3cb1SSiva Durga Prasad Paladugu#include <gicv3.h> 10*f91c3cb1SSiva Durga Prasad Paladugu#include <platform_def.h> 11*f91c3cb1SSiva Durga Prasad Paladugu 12*f91c3cb1SSiva Durga Prasad Paladugu .globl plat_secondary_cold_boot_setup 13*f91c3cb1SSiva Durga Prasad Paladugu .globl plat_is_my_cpu_primary 14*f91c3cb1SSiva Durga Prasad Paladugu .globl versal_calc_core_pos 15*f91c3cb1SSiva Durga Prasad Paladugu .globl platform_mem_init 16*f91c3cb1SSiva Durga Prasad Paladugu .globl plat_my_core_pos 17*f91c3cb1SSiva Durga Prasad Paladugu 18*f91c3cb1SSiva Durga Prasad Paladugu /* ----------------------------------------------------- 19*f91c3cb1SSiva Durga Prasad Paladugu * void plat_secondary_cold_boot_setup (void); 20*f91c3cb1SSiva Durga Prasad Paladugu * 21*f91c3cb1SSiva Durga Prasad Paladugu * This function performs any platform specific actions 22*f91c3cb1SSiva Durga Prasad Paladugu * needed for a secondary cpu after a cold reset e.g 23*f91c3cb1SSiva Durga Prasad Paladugu * mark the cpu's presence, mechanism to place it in a 24*f91c3cb1SSiva Durga Prasad Paladugu * holding pen etc. 25*f91c3cb1SSiva Durga Prasad Paladugu * TODO: Should we read the PSYS register to make sure 26*f91c3cb1SSiva Durga Prasad Paladugu * that the request has gone through. 27*f91c3cb1SSiva Durga Prasad Paladugu * ----------------------------------------------------- 28*f91c3cb1SSiva Durga Prasad Paladugu */ 29*f91c3cb1SSiva Durga Prasad Paladugufunc plat_secondary_cold_boot_setup 30*f91c3cb1SSiva Durga Prasad Paladugu mrs x0, mpidr_el1 31*f91c3cb1SSiva Durga Prasad Paladugu 32*f91c3cb1SSiva Durga Prasad Paladugu /* 33*f91c3cb1SSiva Durga Prasad Paladugu * There is no sane reason to come out of this wfi. This 34*f91c3cb1SSiva Durga Prasad Paladugu * cpu will be powered on and reset by the cpu_on pm api 35*f91c3cb1SSiva Durga Prasad Paladugu */ 36*f91c3cb1SSiva Durga Prasad Paladugu dsb sy 37*f91c3cb1SSiva Durga Prasad Paladugu bl plat_panic_handler 38*f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_secondary_cold_boot_setup 39*f91c3cb1SSiva Durga Prasad Paladugu 40*f91c3cb1SSiva Durga Prasad Paladugufunc plat_is_my_cpu_primary 41*f91c3cb1SSiva Durga Prasad Paladugu mov x9, x30 42*f91c3cb1SSiva Durga Prasad Paladugu bl plat_my_core_pos 43*f91c3cb1SSiva Durga Prasad Paladugu cmp x0, #VERSAL_PRIMARY_CPU 44*f91c3cb1SSiva Durga Prasad Paladugu cset x0, eq 45*f91c3cb1SSiva Durga Prasad Paladugu ret x9 46*f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_is_my_cpu_primary 47*f91c3cb1SSiva Durga Prasad Paladugu 48*f91c3cb1SSiva Durga Prasad Paladugu /* ----------------------------------------------------- 49*f91c3cb1SSiva Durga Prasad Paladugu * unsigned int plat_my_core_pos(void) 50*f91c3cb1SSiva Durga Prasad Paladugu * This function uses the versal_calc_core_pos() 51*f91c3cb1SSiva Durga Prasad Paladugu * definition to get the index of the calling CPU. 52*f91c3cb1SSiva Durga Prasad Paladugu * ----------------------------------------------------- 53*f91c3cb1SSiva Durga Prasad Paladugu */ 54*f91c3cb1SSiva Durga Prasad Paladugufunc plat_my_core_pos 55*f91c3cb1SSiva Durga Prasad Paladugu mrs x0, mpidr_el1 56*f91c3cb1SSiva Durga Prasad Paladugu b versal_calc_core_pos 57*f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_my_core_pos 58*f91c3cb1SSiva Durga Prasad Paladugu 59*f91c3cb1SSiva Durga Prasad Paladugufunc versal_calc_core_pos 60*f91c3cb1SSiva Durga Prasad Paladugu and x1, x0, #MPIDR_CPU_MASK 61*f91c3cb1SSiva Durga Prasad Paladugu and x0, x0, #MPIDR_CLUSTER_MASK 62*f91c3cb1SSiva Durga Prasad Paladugu add x0, x1, x0, LSR #6 63*f91c3cb1SSiva Durga Prasad Paladugu ret 64*f91c3cb1SSiva Durga Prasad Paladuguendfunc versal_calc_core_pos 65*f91c3cb1SSiva Durga Prasad Paladugu 66*f91c3cb1SSiva Durga Prasad Paladugu /* --------------------------------------------------------------------- 67*f91c3cb1SSiva Durga Prasad Paladugu * We don't need to carry out any memory initialization on VERSAL 68*f91c3cb1SSiva Durga Prasad Paladugu * platform. The Secure RAM is accessible straight away. 69*f91c3cb1SSiva Durga Prasad Paladugu * --------------------------------------------------------------------- 70*f91c3cb1SSiva Durga Prasad Paladugu */ 71*f91c3cb1SSiva Durga Prasad Paladugufunc platform_mem_init 72*f91c3cb1SSiva Durga Prasad Paladugu ret 73*f91c3cb1SSiva Durga Prasad Paladuguendfunc platform_mem_init 74