1f91c3cb1SSiva Durga Prasad Paladugu/* 2*619bc13eSMichal Simek * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3f91c3cb1SSiva Durga Prasad Paladugu * 4f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause 5f91c3cb1SSiva Durga Prasad Paladugu */ 6f91c3cb1SSiva Durga Prasad Paladugu 7f91c3cb1SSiva Durga Prasad Paladugu#include <arch.h> 8f91c3cb1SSiva Durga Prasad Paladugu#include <asm_macros.S> 909d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv3.h> 10f91c3cb1SSiva Durga Prasad Paladugu#include <platform_def.h> 11f91c3cb1SSiva Durga Prasad Paladugu 12f91c3cb1SSiva Durga Prasad Paladugu .globl plat_secondary_cold_boot_setup 13f91c3cb1SSiva Durga Prasad Paladugu .globl plat_is_my_cpu_primary 14f91c3cb1SSiva Durga Prasad Paladugu .globl versal_calc_core_pos 15f91c3cb1SSiva Durga Prasad Paladugu .globl platform_mem_init 16f91c3cb1SSiva Durga Prasad Paladugu .globl plat_my_core_pos 17f91c3cb1SSiva Durga Prasad Paladugu 18f91c3cb1SSiva Durga Prasad Paladugu /* ----------------------------------------------------- 19f91c3cb1SSiva Durga Prasad Paladugu * void plat_secondary_cold_boot_setup (void); 20f91c3cb1SSiva Durga Prasad Paladugu * 21f91c3cb1SSiva Durga Prasad Paladugu * This function performs any platform specific actions 22f91c3cb1SSiva Durga Prasad Paladugu * needed for a secondary cpu after a cold reset e.g 23f91c3cb1SSiva Durga Prasad Paladugu * mark the cpu's presence, mechanism to place it in a 24f91c3cb1SSiva Durga Prasad Paladugu * holding pen etc. 25f91c3cb1SSiva Durga Prasad Paladugu * TODO: Should we read the PSYS register to make sure 26f91c3cb1SSiva Durga Prasad Paladugu * that the request has gone through. 27f91c3cb1SSiva Durga Prasad Paladugu * ----------------------------------------------------- 28f91c3cb1SSiva Durga Prasad Paladugu */ 29f91c3cb1SSiva Durga Prasad Paladugufunc plat_secondary_cold_boot_setup 30f91c3cb1SSiva Durga Prasad Paladugu mrs x0, mpidr_el1 31f91c3cb1SSiva Durga Prasad Paladugu 32f91c3cb1SSiva Durga Prasad Paladugu /* 33f91c3cb1SSiva Durga Prasad Paladugu * There is no sane reason to come out of this wfi. This 34f91c3cb1SSiva Durga Prasad Paladugu * cpu will be powered on and reset by the cpu_on pm api 35f91c3cb1SSiva Durga Prasad Paladugu */ 36f91c3cb1SSiva Durga Prasad Paladugu dsb sy 37f91c3cb1SSiva Durga Prasad Paladugu bl plat_panic_handler 38f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_secondary_cold_boot_setup 39f91c3cb1SSiva Durga Prasad Paladugu 40f91c3cb1SSiva Durga Prasad Paladugufunc plat_is_my_cpu_primary 41f91c3cb1SSiva Durga Prasad Paladugu mov x9, x30 42f91c3cb1SSiva Durga Prasad Paladugu bl plat_my_core_pos 43f91c3cb1SSiva Durga Prasad Paladugu cmp x0, #VERSAL_PRIMARY_CPU 44f91c3cb1SSiva Durga Prasad Paladugu cset x0, eq 45f91c3cb1SSiva Durga Prasad Paladugu ret x9 46f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_is_my_cpu_primary 47f91c3cb1SSiva Durga Prasad Paladugu 48f91c3cb1SSiva Durga Prasad Paladugu /* ----------------------------------------------------- 49f91c3cb1SSiva Durga Prasad Paladugu * unsigned int plat_my_core_pos(void) 50f91c3cb1SSiva Durga Prasad Paladugu * This function uses the versal_calc_core_pos() 51f91c3cb1SSiva Durga Prasad Paladugu * definition to get the index of the calling CPU. 52f91c3cb1SSiva Durga Prasad Paladugu * ----------------------------------------------------- 53f91c3cb1SSiva Durga Prasad Paladugu */ 54f91c3cb1SSiva Durga Prasad Paladugufunc plat_my_core_pos 55f91c3cb1SSiva Durga Prasad Paladugu mrs x0, mpidr_el1 56f91c3cb1SSiva Durga Prasad Paladugu b versal_calc_core_pos 57f91c3cb1SSiva Durga Prasad Paladuguendfunc plat_my_core_pos 58f91c3cb1SSiva Durga Prasad Paladugu 59f91c3cb1SSiva Durga Prasad Paladugufunc versal_calc_core_pos 60f91c3cb1SSiva Durga Prasad Paladugu and x1, x0, #MPIDR_CPU_MASK 61f91c3cb1SSiva Durga Prasad Paladugu and x0, x0, #MPIDR_CLUSTER_MASK 62f91c3cb1SSiva Durga Prasad Paladugu add x0, x1, x0, LSR #6 63f91c3cb1SSiva Durga Prasad Paladugu ret 64f91c3cb1SSiva Durga Prasad Paladuguendfunc versal_calc_core_pos 65f91c3cb1SSiva Durga Prasad Paladugu 66f91c3cb1SSiva Durga Prasad Paladugu /* --------------------------------------------------------------------- 67f91c3cb1SSiva Durga Prasad Paladugu * We don't need to carry out any memory initialization on VERSAL 68f91c3cb1SSiva Durga Prasad Paladugu * platform. The Secure RAM is accessible straight away. 69f91c3cb1SSiva Durga Prasad Paladugu * --------------------------------------------------------------------- 70f91c3cb1SSiva Durga Prasad Paladugu */ 71f91c3cb1SSiva Durga Prasad Paladugufunc platform_mem_init 72f91c3cb1SSiva Durga Prasad Paladugu ret 73f91c3cb1SSiva Durga Prasad Paladuguendfunc platform_mem_init 74