1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal power management enums and defines */ 9 10 #ifndef PM_DEFS_H 11 #define PM_DEFS_H 12 13 #include "pm_node.h" 14 15 /********************************************************************* 16 * Macro definitions 17 ********************************************************************/ 18 19 /* State arguments of the self suspend */ 20 #define PM_STATE_CPU_IDLE 0x0U 21 #define PM_STATE_CPU_OFF 0x1U 22 #define PM_STATE_SUSPEND_TO_RAM 0xFU 23 24 #define MAX_LATENCY (~0U) 25 #define MAX_QOS 100U 26 27 /* Processor core device IDs */ 28 #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ 29 XPM_NODETYPE_DEV_CORE_APU, (IDX)) 30 31 #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) 32 #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) 33 34 #define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \ 35 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \ 36 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX)) 37 38 #define TF_A_FEATURE_CHECK 0xa00U 39 #define PM_GET_CALLBACK_DATA 0xa01U 40 #define PM_GET_TRUSTZONE_VERSION 0xa03U 41 #define TF_A_PM_REGISTER_SGI 0xa04U 42 43 /* PM API Versions */ 44 #define PM_API_BASE_VERSION 1U 45 #define PM_API_VERSION_2 2U 46 47 /* Loader API ids */ 48 #define PM_LOAD_PDI 0x701U 49 #define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU 50 51 /* System shutdown macros */ 52 #define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U 53 #define XPM_SHUTDOWN_TYPE_RESET 1U 54 #define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U 55 56 #define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U 57 #define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U 58 #define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U 59 60 /********************************************************************* 61 * Enum definitions 62 ********************************************************************/ 63 64 /* 65 * ioctl id 66 */ 67 enum { 68 IOCTL_GET_RPU_OPER_MODE = 0, 69 IOCTL_SET_RPU_OPER_MODE = 1, 70 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 71 IOCTL_TCM_COMB_CONFIG = 3, 72 IOCTL_SET_TAPDELAY_BYPASS = 4, 73 IOCTL_SD_DLL_RESET = 6, 74 IOCTL_SET_SD_TAPDELAY = 7, 75 /* Ioctl for clock driver */ 76 IOCTL_SET_PLL_FRAC_MODE = 8, 77 IOCTL_GET_PLL_FRAC_MODE = 9, 78 IOCTL_SET_PLL_FRAC_DATA = 10, 79 IOCTL_GET_PLL_FRAC_DATA = 11, 80 IOCTL_WRITE_GGS = 12, 81 IOCTL_READ_GGS = 13, 82 IOCTL_WRITE_PGGS = 14, 83 IOCTL_READ_PGGS = 15, 84 /* IOCTL for ULPI reset */ 85 IOCTL_ULPI_RESET = 16, 86 /* Set healthy bit value */ 87 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 88 IOCTL_AFI = 18, 89 /* Probe counter read/write */ 90 IOCTL_PROBE_COUNTER_READ = 19, 91 IOCTL_PROBE_COUNTER_WRITE = 20, 92 IOCTL_OSPI_MUX_SELECT = 21, 93 /* IOCTL for USB power request */ 94 IOCTL_USB_SET_STATE = 22, 95 /* IOCTL to get last reset reason */ 96 IOCTL_GET_LAST_RESET_REASON = 23, 97 /* AI engine NPI ISR clear */ 98 IOCTL_AIE_ISR_CLEAR = 24, 99 IOCTL_UFS_TXRX_CFGRDY_GET = 40, 100 IOCTL_UFS_SRAM_CSR_SEL = 41, 101 }; 102 103 /** 104 * enum pm_pll_param - enum represents the parameters for a phase-locked loop. 105 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL. 106 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL. 107 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL. 108 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input. 109 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode. 110 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize. 111 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting. 112 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control. 113 * @PM_PLL_PARAM_CP: PLL charge pump control. 114 * @PM_PLL_PARAM_RES: PLL loop filter resistor control. 115 * @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL 116 */ 117 enum pm_pll_param { 118 PM_PLL_PARAM_DIV2, 119 PM_PLL_PARAM_FBDIV, 120 PM_PLL_PARAM_DATA, 121 PM_PLL_PARAM_PRE_SRC, 122 PM_PLL_PARAM_POST_SRC, 123 PM_PLL_PARAM_LOCK_DLY, 124 PM_PLL_PARAM_LOCK_CNT, 125 PM_PLL_PARAM_LFHF, 126 PM_PLL_PARAM_CP, 127 PM_PLL_PARAM_RES, 128 PM_PLL_PARAM_MAX, 129 }; 130 131 enum pm_api_id { 132 /* Miscellaneous API functions: */ 133 PM_GET_API_VERSION = 1, /* Do not change or move */ 134 PM_SET_CONFIGURATION, 135 PM_GET_NODE_STATUS, 136 PM_GET_OP_CHARACTERISTIC, 137 PM_REGISTER_NOTIFIER, 138 /* API for suspending of PUs: */ 139 PM_REQ_SUSPEND, 140 PM_SELF_SUSPEND, 141 PM_FORCE_POWERDOWN, 142 PM_ABORT_SUSPEND, 143 PM_REQ_WAKEUP, 144 PM_SET_WAKEUP_SOURCE, 145 PM_SYSTEM_SHUTDOWN, 146 /* API for managing PM slaves: */ 147 PM_REQ_NODE, 148 PM_RELEASE_NODE, 149 PM_SET_REQUIREMENT, 150 PM_SET_MAX_LATENCY, 151 /* Direct control API functions: */ 152 PM_RESET_ASSERT, 153 PM_RESET_GET_STATUS, 154 PM_MMIO_WRITE, 155 PM_MMIO_READ, 156 PM_INIT_FINALIZE, 157 PM_FPGA_LOAD, 158 PM_FPGA_GET_STATUS, 159 PM_GET_CHIPID, 160 PM_SECURE_RSA_AES, 161 PM_SECURE_SHA, 162 PM_SECURE_RSA, 163 PM_PINCTRL_REQUEST, 164 PM_PINCTRL_RELEASE, 165 PM_PINCTRL_GET_FUNCTION, 166 PM_PINCTRL_SET_FUNCTION, 167 PM_PINCTRL_CONFIG_PARAM_GET, 168 PM_PINCTRL_CONFIG_PARAM_SET, 169 PM_IOCTL, 170 /* API to query information from firmware */ 171 PM_QUERY_DATA, 172 /* Clock control API functions */ 173 PM_CLOCK_ENABLE, 174 PM_CLOCK_DISABLE, 175 PM_CLOCK_GETSTATE, 176 PM_CLOCK_SETDIVIDER, 177 PM_CLOCK_GETDIVIDER, 178 PM_CLOCK_SETPARENT = 43, 179 PM_CLOCK_GETPARENT, 180 PM_SECURE_IMAGE, 181 /* FPGA PL Readback */ 182 PM_FPGA_READ, 183 PM_SECURE_AES, 184 /* PLL control API functions */ 185 PM_PLL_SET_PARAMETER, 186 PM_PLL_GET_PARAMETER, 187 PM_PLL_SET_MODE, 188 PM_PLL_GET_MODE, 189 /* PM Register Access API */ 190 PM_REGISTER_ACCESS, 191 PM_EFUSE_ACCESS, 192 PM_FPGA_GET_VERSION, 193 PM_FPGA_GET_FEATURE_LIST, 194 PM_FEATURE_CHECK = 63, 195 PM_API_MAX = 74 196 }; 197 198 enum pm_abort_reason { 199 ABORT_REASON_WKUP_EVENT = 100, 200 ABORT_REASON_PU_BUSY, 201 ABORT_REASON_NO_PWRDN, 202 ABORT_REASON_UNKNOWN, 203 }; 204 205 enum pm_opchar_type { 206 PM_OPCHAR_TYPE_POWER = 1, 207 PM_OPCHAR_TYPE_TEMP, 208 PM_OPCHAR_TYPE_LATENCY, 209 }; 210 211 /* 212 * Subsystem IDs 213 */ 214 typedef enum { 215 XPM_SUBSYSID_PMC, 216 XPM_SUBSYSID_PSM, 217 XPM_SUBSYSID_APU, 218 XPM_SUBSYSID_RPU0_LOCK, 219 XPM_SUBSYSID_RPU0_0, 220 XPM_SUBSYSID_RPU0_1, 221 XPM_SUBSYSID_DDR0, 222 XPM_SUBSYSID_ME, 223 XPM_SUBSYSID_PL, 224 XPM_SUBSYSID_MAX, 225 } XPm_SubsystemId; 226 227 /* TODO: move pm_ret_status from device specific location to common location */ 228 /** 229 * enum pm_ret_status - enum represents the return status codes for a PM 230 * operation. 231 * @PM_RET_SUCCESS: success. 232 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated). 233 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated). 234 * @PM_RET_ERROR_NOFEATURE: feature is not available. 235 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication. 236 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled. 237 * @PM_RET_ERROR_INTERNAL: internal error. 238 * @PM_RET_ERROR_CONFLICT: conflict. 239 * @PM_RET_ERROR_ACCESS: access rights violation. 240 * @PM_RET_ERROR_INVALID_NODE: invalid node. 241 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node. 242 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted. 243 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU. 244 * @PM_RET_ERROR_NODE_USED: node is already in use. 245 * @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not 246 * supported. 247 */ 248 enum pm_ret_status { 249 PM_RET_SUCCESS, 250 PM_RET_ERROR_ARGS = 1, 251 PM_RET_ERROR_NOTSUPPORTED = 4, 252 PM_RET_ERROR_NOFEATURE = 19, 253 PM_RET_ERROR_INVALID_CRC = 301, 254 PM_RET_ERROR_NOT_ENABLED = 29, 255 PM_RET_ERROR_INTERNAL = 2000, 256 PM_RET_ERROR_CONFLICT = 2001, 257 PM_RET_ERROR_ACCESS = 2002, 258 PM_RET_ERROR_INVALID_NODE = 2003, 259 PM_RET_ERROR_DOUBLE_REQ = 2004, 260 PM_RET_ERROR_ABORT_SUSPEND = 2005, 261 PM_RET_ERROR_TIMEOUT = 2006, 262 PM_RET_ERROR_NODE_USED = 2007, 263 PM_RET_ERROR_NO_FEATURE = 2008 264 }; 265 266 /* 267 * Qids 268 */ 269 enum pm_query_id { 270 XPM_QID_INVALID, 271 XPM_QID_CLOCK_GET_NAME, 272 XPM_QID_CLOCK_GET_TOPOLOGY, 273 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 274 XPM_QID_CLOCK_GET_MUXSOURCES, 275 XPM_QID_CLOCK_GET_ATTRIBUTES, 276 XPM_QID_PINCTRL_GET_NUM_PINS, 277 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS, 278 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 279 XPM_QID_PINCTRL_GET_FUNCTION_NAME, 280 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS, 281 XPM_QID_PINCTRL_GET_PIN_GROUPS, 282 XPM_QID_CLOCK_GET_NUM_CLOCKS, 283 XPM_QID_CLOCK_GET_MAX_DIVISOR, 284 XPM_QID_PLD_GET_PARENT, 285 }; 286 #endif /* PM_DEFS_H */ 287