1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal power management enums and defines */ 9 10 #ifndef PM_DEFS_H 11 #define PM_DEFS_H 12 13 #include "pm_node.h" 14 15 /********************************************************************* 16 * Macro definitions 17 ********************************************************************/ 18 19 /* State arguments of the self suspend */ 20 #define PM_STATE_CPU_IDLE 0x0U 21 #define PM_STATE_CPU_OFF 0x1U 22 #define PM_STATE_SUSPEND_TO_RAM 0xFU 23 24 #define MAX_LATENCY (~0U) 25 26 /* Processor core device IDs */ 27 #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ 28 XPM_NODETYPE_DEV_CORE_APU, (IDX)) 29 30 #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) 31 #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) 32 33 #define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \ 34 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \ 35 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX)) 36 37 #define TF_A_FEATURE_CHECK 0xa00U 38 #define PM_GET_CALLBACK_DATA 0xa01U 39 #define PM_GET_TRUSTZONE_VERSION 0xa03U 40 #define TF_A_PM_REGISTER_SGI 0xa04U 41 42 /* PM API Versions */ 43 #define PM_API_BASE_VERSION 1U 44 #define PM_API_VERSION_2 2U 45 46 /* Loader API ids */ 47 #define PM_LOAD_PDI 0x701U 48 #define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU 49 50 /* System shutdown macros */ 51 #define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U 52 #define XPM_SHUTDOWN_TYPE_RESET 1U 53 #define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U 54 55 #define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U 56 #define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U 57 #define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U 58 59 /********************************************************************* 60 * Enum definitions 61 ********************************************************************/ 62 63 /* 64 * ioctl id 65 */ 66 enum { 67 IOCTL_GET_RPU_OPER_MODE = 0, 68 IOCTL_SET_RPU_OPER_MODE = 1, 69 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 70 IOCTL_TCM_COMB_CONFIG = 3, 71 IOCTL_SET_TAPDELAY_BYPASS = 4, 72 IOCTL_SD_DLL_RESET = 6, 73 IOCTL_SET_SD_TAPDELAY = 7, 74 /* Ioctl for clock driver */ 75 IOCTL_SET_PLL_FRAC_MODE = 8, 76 IOCTL_GET_PLL_FRAC_MODE = 9, 77 IOCTL_SET_PLL_FRAC_DATA = 10, 78 IOCTL_GET_PLL_FRAC_DATA = 11, 79 IOCTL_WRITE_GGS = 12, 80 IOCTL_READ_GGS = 13, 81 IOCTL_WRITE_PGGS = 14, 82 IOCTL_READ_PGGS = 15, 83 /* IOCTL for ULPI reset */ 84 IOCTL_ULPI_RESET = 16, 85 /* Set healthy bit value */ 86 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 87 IOCTL_AFI = 18, 88 /* Probe counter read/write */ 89 IOCTL_PROBE_COUNTER_READ = 19, 90 IOCTL_PROBE_COUNTER_WRITE = 20, 91 IOCTL_OSPI_MUX_SELECT = 21, 92 /* IOCTL for USB power request */ 93 IOCTL_USB_SET_STATE = 22, 94 /* IOCTL to get last reset reason */ 95 IOCTL_GET_LAST_RESET_REASON = 23, 96 /* AI engine NPI ISR clear */ 97 IOCTL_AIE_ISR_CLEAR = 24, 98 IOCTL_UFS_TXRX_CFGRDY_GET = 40, 99 IOCTL_UFS_SRAM_CSR_SEL = 41, 100 }; 101 102 /** 103 * enum pm_pll_param - enum represents the parameters for a phase-locked loop. 104 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL. 105 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL. 106 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL. 107 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input. 108 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode. 109 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize. 110 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting. 111 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control. 112 * @PM_PLL_PARAM_CP: PLL charge pump control. 113 * @PM_PLL_PARAM_RES: PLL loop filter resistor control. 114 * @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL 115 */ 116 enum pm_pll_param { 117 PM_PLL_PARAM_DIV2, 118 PM_PLL_PARAM_FBDIV, 119 PM_PLL_PARAM_DATA, 120 PM_PLL_PARAM_PRE_SRC, 121 PM_PLL_PARAM_POST_SRC, 122 PM_PLL_PARAM_LOCK_DLY, 123 PM_PLL_PARAM_LOCK_CNT, 124 PM_PLL_PARAM_LFHF, 125 PM_PLL_PARAM_CP, 126 PM_PLL_PARAM_RES, 127 PM_PLL_PARAM_MAX, 128 }; 129 130 enum pm_api_id { 131 /* Miscellaneous API functions: */ 132 PM_GET_API_VERSION = 1, /* Do not change or move */ 133 PM_SET_CONFIGURATION, 134 PM_GET_NODE_STATUS, 135 PM_GET_OP_CHARACTERISTIC, 136 PM_REGISTER_NOTIFIER, 137 /* API for suspending of PUs: */ 138 PM_REQ_SUSPEND, 139 PM_SELF_SUSPEND, 140 PM_FORCE_POWERDOWN, 141 PM_ABORT_SUSPEND, 142 PM_REQ_WAKEUP, 143 PM_SET_WAKEUP_SOURCE, 144 PM_SYSTEM_SHUTDOWN, 145 /* API for managing PM slaves: */ 146 PM_REQ_NODE, 147 PM_RELEASE_NODE, 148 PM_SET_REQUIREMENT, 149 PM_SET_MAX_LATENCY, 150 /* Direct control API functions: */ 151 PM_RESET_ASSERT, 152 PM_RESET_GET_STATUS, 153 PM_MMIO_WRITE, 154 PM_MMIO_READ, 155 PM_INIT_FINALIZE, 156 PM_FPGA_LOAD, 157 PM_FPGA_GET_STATUS, 158 PM_GET_CHIPID, 159 PM_SECURE_RSA_AES, 160 PM_SECURE_SHA, 161 PM_SECURE_RSA, 162 PM_PINCTRL_REQUEST, 163 PM_PINCTRL_RELEASE, 164 PM_PINCTRL_GET_FUNCTION, 165 PM_PINCTRL_SET_FUNCTION, 166 PM_PINCTRL_CONFIG_PARAM_GET, 167 PM_PINCTRL_CONFIG_PARAM_SET, 168 PM_IOCTL, 169 /* API to query information from firmware */ 170 PM_QUERY_DATA, 171 /* Clock control API functions */ 172 PM_CLOCK_ENABLE, 173 PM_CLOCK_DISABLE, 174 PM_CLOCK_GETSTATE, 175 PM_CLOCK_SETDIVIDER, 176 PM_CLOCK_GETDIVIDER, 177 PM_CLOCK_SETPARENT = 43, 178 PM_CLOCK_GETPARENT, 179 PM_SECURE_IMAGE, 180 /* FPGA PL Readback */ 181 PM_FPGA_READ, 182 PM_SECURE_AES, 183 /* PLL control API functions */ 184 PM_PLL_SET_PARAMETER, 185 PM_PLL_GET_PARAMETER, 186 PM_PLL_SET_MODE, 187 PM_PLL_GET_MODE, 188 /* PM Register Access API */ 189 PM_REGISTER_ACCESS, 190 PM_EFUSE_ACCESS, 191 PM_FPGA_GET_VERSION, 192 PM_FPGA_GET_FEATURE_LIST, 193 PM_FEATURE_CHECK = 63, 194 PM_API_MAX = 74 195 }; 196 197 enum pm_abort_reason { 198 ABORT_REASON_WKUP_EVENT = 100, 199 ABORT_REASON_PU_BUSY, 200 ABORT_REASON_NO_PWRDN, 201 ABORT_REASON_UNKNOWN, 202 }; 203 204 /* TODO: move pm_ret_status from device specific location to common location */ 205 /** 206 * enum pm_ret_status - enum represents the return status codes for a PM 207 * operation. 208 * @PM_RET_SUCCESS: success. 209 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated). 210 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated). 211 * @PM_RET_ERROR_IOCTL_NOT_SUPPORTED: IOCTL is not supported. 212 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication. 213 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled. 214 * @PM_RET_ERROR_INTERNAL: internal error. 215 * @PM_RET_ERROR_CONFLICT: conflict. 216 * @PM_RET_ERROR_ACCESS: access rights violation. 217 * @PM_RET_ERROR_INVALID_NODE: invalid node. 218 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node. 219 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted. 220 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU. 221 * @PM_RET_ERROR_NODE_USED: node is already in use. 222 * @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not 223 * supported. 224 */ 225 enum pm_ret_status { 226 PM_RET_SUCCESS = 0U, 227 PM_RET_ERROR_ARGS = 1U, 228 PM_RET_ERROR_NOTSUPPORTED = 4U, 229 PM_RET_ERROR_IOCTL_NOT_SUPPORTED = 19U, 230 PM_RET_ERROR_NOT_ENABLED = 29U, 231 PM_RET_ERROR_INVALID_CRC = 301U, 232 PM_RET_ERROR_INTERNAL = 2000U, 233 PM_RET_ERROR_CONFLICT = 2001U, 234 PM_RET_ERROR_ACCESS = 2002U, 235 PM_RET_ERROR_INVALID_NODE = 2003U, 236 PM_RET_ERROR_DOUBLE_REQ = 2004U, 237 PM_RET_ERROR_ABORT_SUSPEND = 2005U, 238 PM_RET_ERROR_TIMEOUT = 2006U, 239 PM_RET_ERROR_NODE_USED = 2007U, 240 PM_RET_ERROR_NO_FEATURE = 2008U 241 }; 242 243 /* 244 * Qids 245 */ 246 enum pm_query_id { 247 XPM_QID_INVALID, 248 XPM_QID_CLOCK_GET_NAME, 249 XPM_QID_CLOCK_GET_TOPOLOGY, 250 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 251 XPM_QID_CLOCK_GET_MUXSOURCES, 252 XPM_QID_CLOCK_GET_ATTRIBUTES, 253 XPM_QID_PINCTRL_GET_NUM_PINS, 254 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS, 255 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 256 XPM_QID_PINCTRL_GET_FUNCTION_NAME, 257 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS, 258 XPM_QID_PINCTRL_GET_PIN_GROUPS, 259 XPM_QID_CLOCK_GET_NUM_CLOCKS, 260 XPM_QID_CLOCK_GET_MAX_DIVISOR, 261 XPM_QID_PLD_GET_PARENT, 262 }; 263 #endif /* PM_DEFS_H */ 264