1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <board_def.h> 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stack */ 20 #if IMAGE_BL31 21 #define PLATFORM_STACK_SIZE 0x800 22 #else 23 #define PLATFORM_STACK_SIZE 0x1000 24 #endif 25 26 #define PLATFORM_SYSTEM_COUNT 1 27 #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 28 K3_CLUSTER1_CORE_COUNT + \ 29 K3_CLUSTER2_CORE_COUNT + \ 30 K3_CLUSTER3_CORE_COUNT) 31 32 #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ 33 (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ 34 (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ 35 (K3_CLUSTER3_MSMC_PORT != UNUSED)) 36 37 #define UNUSED -1 38 39 #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) 40 #define K3_CLUSTER1_CORE_COUNT 0 41 #define K3_CLUSTER1_MSMC_PORT UNUSED 42 #endif 43 44 #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) 45 #define K3_CLUSTER2_CORE_COUNT 0 46 #define K3_CLUSTER2_MSMC_PORT UNUSED 47 #endif 48 49 #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) 50 #define K3_CLUSTER3_CORE_COUNT 0 51 #define K3_CLUSTER3_MSMC_PORT UNUSED 52 #endif 53 54 #if K3_CLUSTER0_MSMC_PORT == UNUSED 55 #error "ARM cluster 0 must be used" 56 #endif 57 58 #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ 59 ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ 60 ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) 61 #error "Unused ports must have 0 ARM cores" 62 #endif 63 64 #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT 65 66 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 67 PLATFORM_CLUSTER_COUNT + \ 68 PLATFORM_CORE_COUNT) 69 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 70 71 /******************************************************************************* 72 * Memory layout constants 73 ******************************************************************************/ 74 75 /* 76 * ARM-TF lives in SRAM, partition it here 77 * 78 * BL3-1 specific defines. 79 * 80 * Put BL3-1 at the base of the Trusted SRAM. 81 */ 82 #define BL31_BASE SEC_SRAM_BASE 83 #define BL31_SIZE SEC_SRAM_SIZE 84 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 85 86 /* 87 * Defines the maximum number of translation tables that are allocated by the 88 * translation table library code. To minimize the amount of runtime memory 89 * used, choose the smallest value needed to map the required virtual addresses 90 * for each BL stage. 91 */ 92 #define MAX_XLAT_TABLES 8 93 94 /* 95 * Defines the maximum number of regions that are allocated by the translation 96 * table library code. A region consists of physical base address, virtual base 97 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 98 * defined in the `mmap_region_t` structure. The platform defines the regions 99 * that should be mapped. Then, the translation table library will create the 100 * corresponding tables and descriptors at runtime. To minimize the amount of 101 * runtime memory used, choose the smallest value needed to register the 102 * required regions for each BL stage. 103 */ 104 #define MAX_MMAP_REGIONS 11 105 106 /* 107 * Defines the total size of the address space in bytes. For example, for a 32 108 * bit address space, this value should be `(1ull << 32)`. 109 */ 110 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 111 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 112 113 /* 114 * Some data must be aligned on the biggest cache line size in the platform. 115 * This is known only to the platform as it might have a combination of 116 * integrated and external caches. 117 */ 118 #define CACHE_WRITEBACK_SHIFT 6 119 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 120 121 /* Platform default console definitions */ 122 #ifndef K3_USART_BASE 123 #define K3_USART_BASE 0x02800000 124 #endif 125 126 /* USART has a default size for address space */ 127 #define K3_USART_SIZE 0x1000 128 129 #ifndef K3_USART_CLK_SPEED 130 #define K3_USART_CLK_SPEED 48000000 131 #endif 132 133 /* Crash console defaults */ 134 #define CRASH_CONSOLE_BASE K3_USART_BASE 135 #define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED 136 #define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD 137 138 /* Timer frequency */ 139 #ifndef SYS_COUNTER_FREQ_IN_TICKS 140 #define SYS_COUNTER_FREQ_IN_TICKS 200000000 141 #endif 142 143 /* Interrupt numbers */ 144 #define ARM_IRQ_SEC_PHY_TIMER 29 145 146 #define ARM_IRQ_SEC_SGI_0 8 147 #define ARM_IRQ_SEC_SGI_1 9 148 #define ARM_IRQ_SEC_SGI_2 10 149 #define ARM_IRQ_SEC_SGI_3 11 150 #define ARM_IRQ_SEC_SGI_4 12 151 #define ARM_IRQ_SEC_SGI_5 13 152 #define ARM_IRQ_SEC_SGI_6 14 153 #define ARM_IRQ_SEC_SGI_7 15 154 155 /* 156 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 157 * terminology. On a GICv2 system or mode, the lists will be merged and treated 158 * as Group 0 interrupts. 159 */ 160 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 161 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 162 GIC_INTR_CFG_LEVEL), \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 164 GIC_INTR_CFG_EDGE), \ 165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 166 GIC_INTR_CFG_EDGE), \ 167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 168 GIC_INTR_CFG_EDGE), \ 169 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 170 GIC_INTR_CFG_EDGE), \ 171 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 172 GIC_INTR_CFG_EDGE), \ 173 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 174 GIC_INTR_CFG_EDGE) 175 176 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 177 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 178 GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 180 GIC_INTR_CFG_EDGE) 181 182 #define K3_GIC_BASE 0x01800000 183 #define K3_GIC_SIZE 0x200000 184 185 #define SEC_PROXY_DATA_BASE 0x32C00000 186 #define SEC_PROXY_DATA_SIZE 0x80000 187 #define SEC_PROXY_SCFG_BASE 0x32800000 188 #define SEC_PROXY_SCFG_SIZE 0x80000 189 #define SEC_PROXY_RT_BASE 0x32400000 190 #define SEC_PROXY_RT_SIZE 0x80000 191 192 #define SEC_PROXY_TIMEOUT_US 1000000 193 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 194 195 #define TI_SCI_HOST_ID 10 196 #define TI_SCI_MAX_MESSAGE_SIZE 52 197 198 #endif /* PLATFORM_DEF_H */ 199