1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <board_def.h> 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stack */ 20 #if IMAGE_BL31 21 #define PLATFORM_STACK_SIZE 0x800 22 #else 23 #define PLATFORM_STACK_SIZE 0x1000 24 #endif 25 26 #define PLATFORM_SYSTEM_COUNT 1 27 #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 28 K3_CLUSTER1_CORE_COUNT + \ 29 K3_CLUSTER2_CORE_COUNT + \ 30 K3_CLUSTER3_CORE_COUNT) 31 32 #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ 33 (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ 34 (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ 35 (K3_CLUSTER3_MSMC_PORT != UNUSED)) 36 37 #define UNUSED -1 38 39 #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) 40 #define K3_CLUSTER1_CORE_COUNT 0 41 #define K3_CLUSTER1_MSMC_PORT UNUSED 42 #endif 43 44 #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) 45 #define K3_CLUSTER2_CORE_COUNT 0 46 #define K3_CLUSTER2_MSMC_PORT UNUSED 47 #endif 48 49 #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) 50 #define K3_CLUSTER3_CORE_COUNT 0 51 #define K3_CLUSTER3_MSMC_PORT UNUSED 52 #endif 53 54 #if K3_CLUSTER0_MSMC_PORT == UNUSED 55 #error "ARM cluster 0 must be used" 56 #endif 57 58 #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ 59 ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ 60 ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) 61 #error "Unused ports must have 0 ARM cores" 62 #endif 63 64 #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT 65 66 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 67 PLATFORM_CLUSTER_COUNT + \ 68 PLATFORM_CORE_COUNT) 69 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 70 71 /******************************************************************************* 72 * Memory layout constants 73 ******************************************************************************/ 74 75 /* 76 * ARM-TF lives in SRAM, partition it here 77 */ 78 79 #define SHARED_RAM_BASE BL31_LIMIT 80 #define SHARED_RAM_SIZE 0x00001000 81 82 /* 83 * BL3-1 specific defines. 84 * 85 * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. 86 */ 87 #define BL31_BASE SEC_SRAM_BASE 88 #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 89 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 90 #define BL31_PROGBITS_LIMIT BL31_LIMIT 91 92 /* 93 * Defines the maximum number of translation tables that are allocated by the 94 * translation table library code. To minimize the amount of runtime memory 95 * used, choose the smallest value needed to map the required virtual addresses 96 * for each BL stage. 97 */ 98 #define MAX_XLAT_TABLES 8 99 100 /* 101 * Defines the maximum number of regions that are allocated by the translation 102 * table library code. A region consists of physical base address, virtual base 103 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 104 * defined in the `mmap_region_t` structure. The platform defines the regions 105 * that should be mapped. Then, the translation table library will create the 106 * corresponding tables and descriptors at runtime. To minimize the amount of 107 * runtime memory used, choose the smallest value needed to register the 108 * required regions for each BL stage. 109 */ 110 #define MAX_MMAP_REGIONS 11 111 112 /* 113 * Defines the total size of the address space in bytes. For example, for a 32 114 * bit address space, this value should be `(1ull << 32)`. 115 */ 116 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 117 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 118 119 /* 120 * Some data must be aligned on the biggest cache line size in the platform. 121 * This is known only to the platform as it might have a combination of 122 * integrated and external caches. 123 */ 124 #define CACHE_WRITEBACK_SHIFT 6 125 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 126 127 /* Platform default console definitions */ 128 #ifndef K3_USART_BASE_ADDRESS 129 #define K3_USART_BASE_ADDRESS 0x02800000 130 #endif 131 132 /* USART has a default size for address space */ 133 #define K3_USART_SIZE 0x1000 134 135 #ifndef K3_USART_CLK_SPEED 136 #define K3_USART_CLK_SPEED 48000000 137 #endif 138 139 #ifndef K3_USART_BAUD 140 #define K3_USART_BAUD 115200 141 #endif 142 143 /* Crash console defaults */ 144 #define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS 145 #define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED 146 #define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD 147 148 /* Timer frequency */ 149 #ifndef SYS_COUNTER_FREQ_IN_TICKS 150 #define SYS_COUNTER_FREQ_IN_TICKS 200000000 151 #endif 152 153 /* Interrupt numbers */ 154 #define ARM_IRQ_SEC_PHY_TIMER 29 155 156 #define ARM_IRQ_SEC_SGI_0 8 157 #define ARM_IRQ_SEC_SGI_1 9 158 #define ARM_IRQ_SEC_SGI_2 10 159 #define ARM_IRQ_SEC_SGI_3 11 160 #define ARM_IRQ_SEC_SGI_4 12 161 #define ARM_IRQ_SEC_SGI_5 13 162 #define ARM_IRQ_SEC_SGI_6 14 163 #define ARM_IRQ_SEC_SGI_7 15 164 165 /* 166 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 167 * terminology. On a GICv2 system or mode, the lists will be merged and treated 168 * as Group 0 interrupts. 169 */ 170 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 171 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 172 GIC_INTR_CFG_LEVEL), \ 173 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 174 GIC_INTR_CFG_EDGE), \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 176 GIC_INTR_CFG_EDGE), \ 177 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 178 GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 180 GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 182 GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 184 GIC_INTR_CFG_EDGE) 185 186 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 187 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 188 GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 190 GIC_INTR_CFG_EDGE) 191 192 #define K3_GICD_BASE 0x01800000 193 #define K3_GICD_SIZE 0x10000 194 #define K3_GICR_BASE 0x01880000 195 #define K3_GICR_SIZE 0x100000 196 197 #define SEC_PROXY_DATA_BASE 0x32C00000 198 #define SEC_PROXY_DATA_SIZE 0x80000 199 #define SEC_PROXY_SCFG_BASE 0x32800000 200 #define SEC_PROXY_SCFG_SIZE 0x80000 201 #define SEC_PROXY_RT_BASE 0x32400000 202 #define SEC_PROXY_RT_SIZE 0x80000 203 204 #define SEC_PROXY_TIMEOUT_US 1000000 205 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 206 207 #define TI_SCI_HOST_ID 10 208 #define TI_SCI_MAX_MESSAGE_SIZE 52 209 210 #endif /* PLATFORM_DEF_H */ 211