1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <board_def.h> 12 #include <common_def.h> 13 14 /******************************************************************************* 15 * Generic platform constants 16 ******************************************************************************/ 17 18 /* Size of cacheable stack */ 19 #if IMAGE_BL31 20 #define PLATFORM_STACK_SIZE 0x800 21 #else 22 #define PLATFORM_STACK_SIZE 0x1000 23 #endif 24 25 #define PLATFORM_SYSTEM_COUNT 1 26 #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 27 K3_CLUSTER1_CORE_COUNT + \ 28 K3_CLUSTER2_CORE_COUNT + \ 29 K3_CLUSTER3_CORE_COUNT) 30 31 #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ 32 (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ 33 (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ 34 (K3_CLUSTER3_MSMC_PORT != UNUSED)) 35 36 #define UNUSED -1 37 38 #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) 39 #define K3_CLUSTER1_CORE_COUNT 0 40 #define K3_CLUSTER1_MSMC_PORT UNUSED 41 #endif 42 43 #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) 44 #define K3_CLUSTER2_CORE_COUNT 0 45 #define K3_CLUSTER2_MSMC_PORT UNUSED 46 #endif 47 48 #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) 49 #define K3_CLUSTER3_CORE_COUNT 0 50 #define K3_CLUSTER3_MSMC_PORT UNUSED 51 #endif 52 53 #if K3_CLUSTER0_MSMC_PORT == UNUSED 54 #error "ARM cluster 0 must be used" 55 #endif 56 57 #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ 58 ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ 59 ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) 60 #error "Unused ports must have 0 ARM cores" 61 #endif 62 63 #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT 64 65 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 66 PLATFORM_CORE_COUNT) 67 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 68 69 /******************************************************************************* 70 * Memory layout constants 71 ******************************************************************************/ 72 73 /* 74 * ARM-TF lives in SRAM, partition it here 75 */ 76 77 #define SHARED_RAM_BASE BL31_LIMIT 78 #define SHARED_RAM_SIZE 0x00001000 79 80 /* 81 * BL3-1 specific defines. 82 * 83 * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. 84 */ 85 #define BL31_BASE SEC_SRAM_BASE 86 #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 87 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 88 #define BL31_PROGBITS_LIMIT BL31_LIMIT 89 90 /* 91 * Some data must be aligned on the biggest cache line size in the platform. 92 * This is known only to the platform as it might have a combination of 93 * integrated and external caches. 94 */ 95 #define CACHE_WRITEBACK_SHIFT 6 96 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 97 98 #endif /* __PLATFORM_DEF_H__ */ 99