1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <board_def.h> 12 #include <common_def.h> 13 14 /******************************************************************************* 15 * Generic platform constants 16 ******************************************************************************/ 17 18 /* Size of cacheable stack */ 19 #if IMAGE_BL31 20 #define PLATFORM_STACK_SIZE 0x800 21 #else 22 #define PLATFORM_STACK_SIZE 0x1000 23 #endif 24 25 #define PLATFORM_SYSTEM_COUNT 1 26 #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 27 K3_CLUSTER1_CORE_COUNT + \ 28 K3_CLUSTER2_CORE_COUNT + \ 29 K3_CLUSTER3_CORE_COUNT) 30 31 #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ 32 (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ 33 (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ 34 (K3_CLUSTER3_MSMC_PORT != UNUSED)) 35 36 #define UNUSED -1 37 38 #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) 39 #define K3_CLUSTER1_CORE_COUNT 0 40 #define K3_CLUSTER1_MSMC_PORT UNUSED 41 #endif 42 43 #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) 44 #define K3_CLUSTER2_CORE_COUNT 0 45 #define K3_CLUSTER2_MSMC_PORT UNUSED 46 #endif 47 48 #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) 49 #define K3_CLUSTER3_CORE_COUNT 0 50 #define K3_CLUSTER3_MSMC_PORT UNUSED 51 #endif 52 53 #if K3_CLUSTER0_MSMC_PORT == UNUSED 54 #error "ARM cluster 0 must be used" 55 #endif 56 57 #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ 58 ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ 59 ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) 60 #error "Unused ports must have 0 ARM cores" 61 #endif 62 63 #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT 64 65 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 66 PLATFORM_CLUSTER_COUNT + \ 67 PLATFORM_CORE_COUNT) 68 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 69 70 /******************************************************************************* 71 * Memory layout constants 72 ******************************************************************************/ 73 74 /* 75 * ARM-TF lives in SRAM, partition it here 76 */ 77 78 #define SHARED_RAM_BASE BL31_LIMIT 79 #define SHARED_RAM_SIZE 0x00001000 80 81 /* 82 * BL3-1 specific defines. 83 * 84 * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. 85 */ 86 #define BL31_BASE SEC_SRAM_BASE 87 #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 88 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 89 #define BL31_PROGBITS_LIMIT BL31_LIMIT 90 91 /* 92 * Defines the maximum number of translation tables that are allocated by the 93 * translation table library code. To minimize the amount of runtime memory 94 * used, choose the smallest value needed to map the required virtual addresses 95 * for each BL stage. 96 */ 97 #define MAX_XLAT_TABLES 8 98 99 /* 100 * Defines the maximum number of regions that are allocated by the translation 101 * table library code. A region consists of physical base address, virtual base 102 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 103 * defined in the `mmap_region_t` structure. The platform defines the regions 104 * that should be mapped. Then, the translation table library will create the 105 * corresponding tables and descriptors at runtime. To minimize the amount of 106 * runtime memory used, choose the smallest value needed to register the 107 * required regions for each BL stage. 108 */ 109 #define MAX_MMAP_REGIONS 11 110 111 /* 112 * Defines the total size of the address space in bytes. For example, for a 32 113 * bit address space, this value should be `(1ull << 32)`. 114 */ 115 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 116 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 117 118 /* 119 * Some data must be aligned on the biggest cache line size in the platform. 120 * This is known only to the platform as it might have a combination of 121 * integrated and external caches. 122 */ 123 #define CACHE_WRITEBACK_SHIFT 6 124 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 125 126 /* Platform default console definitions */ 127 #ifndef K3_USART_BASE_ADDRESS 128 #define K3_USART_BASE_ADDRESS 0x02800000 129 #endif 130 131 /* USART has a default size for address space */ 132 #define K3_USART_SIZE 0x1000 133 134 #ifndef K3_USART_CLK_SPEED 135 #define K3_USART_CLK_SPEED 48000000 136 #endif 137 138 #ifndef K3_USART_BAUD 139 #define K3_USART_BAUD 115200 140 #endif 141 142 /* Crash console defaults */ 143 #define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS 144 #define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED 145 #define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD 146 147 /* Timer frequency */ 148 #ifndef SYS_COUNTER_FREQ_IN_TICKS 149 #define SYS_COUNTER_FREQ_IN_TICKS 200000000 150 #endif 151 152 /* Interrupt numbers */ 153 #define ARM_IRQ_SEC_PHY_TIMER 29 154 155 #define ARM_IRQ_SEC_SGI_0 8 156 #define ARM_IRQ_SEC_SGI_1 9 157 #define ARM_IRQ_SEC_SGI_2 10 158 #define ARM_IRQ_SEC_SGI_3 11 159 #define ARM_IRQ_SEC_SGI_4 12 160 #define ARM_IRQ_SEC_SGI_5 13 161 #define ARM_IRQ_SEC_SGI_6 14 162 #define ARM_IRQ_SEC_SGI_7 15 163 164 /* 165 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 166 * terminology. On a GICv2 system or mode, the lists will be merged and treated 167 * as Group 0 interrupts. 168 */ 169 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 170 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 171 GIC_INTR_CFG_LEVEL), \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 173 GIC_INTR_CFG_EDGE), \ 174 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 175 GIC_INTR_CFG_EDGE), \ 176 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 177 GIC_INTR_CFG_EDGE), \ 178 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 179 GIC_INTR_CFG_EDGE), \ 180 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 181 GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 183 GIC_INTR_CFG_EDGE) 184 185 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 186 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 187 GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 189 GIC_INTR_CFG_EDGE) 190 191 #define K3_GICD_BASE 0x01800000 192 #define K3_GICD_SIZE 0x10000 193 #define K3_GICR_BASE 0x01880000 194 #define K3_GICR_SIZE 0x100000 195 196 #define SEC_PROXY_DATA_BASE 0x32C00000 197 #define SEC_PROXY_DATA_SIZE 0x80000 198 #define SEC_PROXY_SCFG_BASE 0x32800000 199 #define SEC_PROXY_SCFG_SIZE 0x80000 200 #define SEC_PROXY_RT_BASE 0x32400000 201 #define SEC_PROXY_RT_SIZE 0x80000 202 203 #define SEC_PROXY_TIMEOUT_US 1000000 204 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 205 206 #define TI_SCI_HOST_ID 10 207 #define TI_SCI_MAX_MESSAGE_SIZE 52 208 209 #endif /* __PLATFORM_DEF_H__ */ 210