11841c533SNishanth Menon /* 21841c533SNishanth Menon * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 31841c533SNishanth Menon * 41841c533SNishanth Menon * SPDX-License-Identifier: BSD-3-Clause 51841c533SNishanth Menon */ 61841c533SNishanth Menon 71841c533SNishanth Menon #ifndef __PLATFORM_DEF_H__ 81841c533SNishanth Menon #define __PLATFORM_DEF_H__ 91841c533SNishanth Menon 101841c533SNishanth Menon #include <arch.h> 111841c533SNishanth Menon #include <board_def.h> 121841c533SNishanth Menon #include <common_def.h> 131841c533SNishanth Menon 141841c533SNishanth Menon /******************************************************************************* 151841c533SNishanth Menon * Generic platform constants 161841c533SNishanth Menon ******************************************************************************/ 171841c533SNishanth Menon 181841c533SNishanth Menon /* Size of cacheable stack */ 191841c533SNishanth Menon #if IMAGE_BL31 201841c533SNishanth Menon #define PLATFORM_STACK_SIZE 0x800 211841c533SNishanth Menon #else 221841c533SNishanth Menon #define PLATFORM_STACK_SIZE 0x1000 231841c533SNishanth Menon #endif 241841c533SNishanth Menon 25*89574715SBenjamin Fair #define PLATFORM_SYSTEM_COUNT 1 26*89574715SBenjamin Fair #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 27*89574715SBenjamin Fair K3_CLUSTER1_CORE_COUNT + \ 28*89574715SBenjamin Fair K3_CLUSTER2_CORE_COUNT + \ 29*89574715SBenjamin Fair K3_CLUSTER3_CORE_COUNT) 30*89574715SBenjamin Fair 31*89574715SBenjamin Fair #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ 32*89574715SBenjamin Fair (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ 33*89574715SBenjamin Fair (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ 34*89574715SBenjamin Fair (K3_CLUSTER3_MSMC_PORT != UNUSED)) 35*89574715SBenjamin Fair 36*89574715SBenjamin Fair #define UNUSED -1 37*89574715SBenjamin Fair 38*89574715SBenjamin Fair #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) 39*89574715SBenjamin Fair #define K3_CLUSTER1_CORE_COUNT 0 40*89574715SBenjamin Fair #define K3_CLUSTER1_MSMC_PORT UNUSED 41*89574715SBenjamin Fair #endif 42*89574715SBenjamin Fair 43*89574715SBenjamin Fair #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) 44*89574715SBenjamin Fair #define K3_CLUSTER2_CORE_COUNT 0 45*89574715SBenjamin Fair #define K3_CLUSTER2_MSMC_PORT UNUSED 46*89574715SBenjamin Fair #endif 47*89574715SBenjamin Fair 48*89574715SBenjamin Fair #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) 49*89574715SBenjamin Fair #define K3_CLUSTER3_CORE_COUNT 0 50*89574715SBenjamin Fair #define K3_CLUSTER3_MSMC_PORT UNUSED 51*89574715SBenjamin Fair #endif 52*89574715SBenjamin Fair 53*89574715SBenjamin Fair #if K3_CLUSTER0_MSMC_PORT == UNUSED 54*89574715SBenjamin Fair #error "ARM cluster 0 must be used" 55*89574715SBenjamin Fair #endif 56*89574715SBenjamin Fair 57*89574715SBenjamin Fair #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ 58*89574715SBenjamin Fair ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ 59*89574715SBenjamin Fair ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) 60*89574715SBenjamin Fair #error "Unused ports must have 0 ARM cores" 61*89574715SBenjamin Fair #endif 62*89574715SBenjamin Fair 63*89574715SBenjamin Fair #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT 64*89574715SBenjamin Fair 651841c533SNishanth Menon #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 661841c533SNishanth Menon PLATFORM_CORE_COUNT) 671841c533SNishanth Menon #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 681841c533SNishanth Menon 691841c533SNishanth Menon /******************************************************************************* 701841c533SNishanth Menon * Memory layout constants 711841c533SNishanth Menon ******************************************************************************/ 721841c533SNishanth Menon 731841c533SNishanth Menon /* 741841c533SNishanth Menon * ARM-TF lives in SRAM, partition it here 751841c533SNishanth Menon */ 761841c533SNishanth Menon 771841c533SNishanth Menon #define SHARED_RAM_BASE BL31_LIMIT 781841c533SNishanth Menon #define SHARED_RAM_SIZE 0x00001000 791841c533SNishanth Menon 801841c533SNishanth Menon /* 811841c533SNishanth Menon * BL3-1 specific defines. 821841c533SNishanth Menon * 831841c533SNishanth Menon * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. 841841c533SNishanth Menon */ 851841c533SNishanth Menon #define BL31_BASE SEC_SRAM_BASE 861841c533SNishanth Menon #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 871841c533SNishanth Menon #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 881841c533SNishanth Menon #define BL31_PROGBITS_LIMIT BL31_LIMIT 891841c533SNishanth Menon 901841c533SNishanth Menon /* 911841c533SNishanth Menon * Some data must be aligned on the biggest cache line size in the platform. 921841c533SNishanth Menon * This is known only to the platform as it might have a combination of 931841c533SNishanth Menon * integrated and external caches. 941841c533SNishanth Menon */ 951841c533SNishanth Menon #define CACHE_WRITEBACK_SHIFT 6 961841c533SNishanth Menon #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 971841c533SNishanth Menon 981841c533SNishanth Menon #endif /* __PLATFORM_DEF_H__ */ 99