1*1841c533SNishanth Menon /* 2*1841c533SNishanth Menon * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*1841c533SNishanth Menon * 4*1841c533SNishanth Menon * SPDX-License-Identifier: BSD-3-Clause 5*1841c533SNishanth Menon */ 6*1841c533SNishanth Menon 7*1841c533SNishanth Menon #ifndef __PLATFORM_DEF_H__ 8*1841c533SNishanth Menon #define __PLATFORM_DEF_H__ 9*1841c533SNishanth Menon 10*1841c533SNishanth Menon #include <arch.h> 11*1841c533SNishanth Menon #include <board_def.h> 12*1841c533SNishanth Menon #include <common_def.h> 13*1841c533SNishanth Menon 14*1841c533SNishanth Menon /******************************************************************************* 15*1841c533SNishanth Menon * Generic platform constants 16*1841c533SNishanth Menon ******************************************************************************/ 17*1841c533SNishanth Menon 18*1841c533SNishanth Menon /* Size of cacheable stack */ 19*1841c533SNishanth Menon #if IMAGE_BL31 20*1841c533SNishanth Menon #define PLATFORM_STACK_SIZE 0x800 21*1841c533SNishanth Menon #else 22*1841c533SNishanth Menon #define PLATFORM_STACK_SIZE 0x1000 23*1841c533SNishanth Menon #endif 24*1841c533SNishanth Menon 25*1841c533SNishanth Menon #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 26*1841c533SNishanth Menon PLATFORM_CORE_COUNT) 27*1841c533SNishanth Menon #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 28*1841c533SNishanth Menon 29*1841c533SNishanth Menon /******************************************************************************* 30*1841c533SNishanth Menon * Memory layout constants 31*1841c533SNishanth Menon ******************************************************************************/ 32*1841c533SNishanth Menon 33*1841c533SNishanth Menon /* 34*1841c533SNishanth Menon * ARM-TF lives in SRAM, partition it here 35*1841c533SNishanth Menon */ 36*1841c533SNishanth Menon 37*1841c533SNishanth Menon #define SHARED_RAM_BASE BL31_LIMIT 38*1841c533SNishanth Menon #define SHARED_RAM_SIZE 0x00001000 39*1841c533SNishanth Menon 40*1841c533SNishanth Menon /* 41*1841c533SNishanth Menon * BL3-1 specific defines. 42*1841c533SNishanth Menon * 43*1841c533SNishanth Menon * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. 44*1841c533SNishanth Menon */ 45*1841c533SNishanth Menon #define BL31_BASE SEC_SRAM_BASE 46*1841c533SNishanth Menon #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 47*1841c533SNishanth Menon #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 48*1841c533SNishanth Menon #define BL31_PROGBITS_LIMIT BL31_LIMIT 49*1841c533SNishanth Menon 50*1841c533SNishanth Menon /* 51*1841c533SNishanth Menon * Some data must be aligned on the biggest cache line size in the platform. 52*1841c533SNishanth Menon * This is known only to the platform as it might have a combination of 53*1841c533SNishanth Menon * integrated and external caches. 54*1841c533SNishanth Menon */ 55*1841c533SNishanth Menon #define CACHE_WRITEBACK_SHIFT 6 56*1841c533SNishanth Menon #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 57*1841c533SNishanth Menon 58*1841c533SNishanth Menon #endif /* __PLATFORM_DEF_H__ */ 59