1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <k3_gicv3.h> 11 #include <psci.h> 12 #include <platform.h> 13 #include <stdbool.h> 14 15 #include <ti_sci.h> 16 17 #define STUB() ERROR("stub %s called\n", __func__) 18 19 uintptr_t k3_sec_entrypoint; 20 21 static void k3_cpu_standby(plat_local_state_t cpu_state) 22 { 23 unsigned int scr; 24 25 scr = read_scr_el3(); 26 /* Enable the Non secure interrupt to wake the CPU */ 27 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 28 isb(); 29 /* dsb is good practice before using wfi to enter low power states */ 30 dsb(); 31 /* Enter standby state */ 32 wfi(); 33 /* Restore SCR */ 34 write_scr_el3(scr); 35 } 36 37 static int k3_pwr_domain_on(u_register_t mpidr) 38 { 39 int core_id, proc, device, ret; 40 41 core_id = plat_core_pos_by_mpidr(mpidr); 42 if (core_id < 0) { 43 ERROR("Could not get target core id: %d\n", core_id); 44 return PSCI_E_INTERN_FAIL; 45 } 46 47 proc = PLAT_PROC_START_ID + core_id; 48 device = PLAT_PROC_DEVICE_START_ID + core_id; 49 50 ret = ti_sci_proc_request(proc); 51 if (ret) { 52 ERROR("Request for processor failed: %d\n", ret); 53 return PSCI_E_INTERN_FAIL; 54 } 55 56 ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0); 57 if (ret) { 58 ERROR("Request to set core boot address failed: %d\n", ret); 59 return PSCI_E_INTERN_FAIL; 60 } 61 62 ret = ti_sci_device_get(device); 63 if (ret) { 64 ERROR("Request to start core failed: %d\n", ret); 65 return PSCI_E_INTERN_FAIL; 66 } 67 68 ret = ti_sci_proc_release(proc); 69 if (ret) { 70 /* this is not fatal */ 71 WARN("Could not release processor control: %d\n", ret); 72 } 73 74 return PSCI_E_SUCCESS; 75 } 76 77 void k3_pwr_domain_off(const psci_power_state_t *target_state) 78 { 79 /* Prevent interrupts from spuriously waking up this cpu */ 80 k3_gic_cpuif_disable(); 81 82 /* TODO: Indicate to System firmware about powering down */ 83 } 84 85 void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) 86 { 87 /* TODO: Indicate to System firmware about completion */ 88 89 k3_gic_pcpu_init(); 90 k3_gic_cpuif_enable(); 91 } 92 93 static void __dead2 k3_system_reset(void) 94 { 95 /* Send the system reset request to system firmware */ 96 ti_sci_core_reboot(); 97 98 while (true) 99 wfi(); 100 } 101 102 static int k3_validate_power_state(unsigned int power_state, 103 psci_power_state_t *req_state) 104 { 105 /* TODO: perform the proper validation */ 106 107 return PSCI_E_SUCCESS; 108 } 109 110 static int k3_validate_ns_entrypoint(uintptr_t entrypoint) 111 { 112 /* TODO: perform the proper validation */ 113 114 return PSCI_E_SUCCESS; 115 } 116 117 static const plat_psci_ops_t k3_plat_psci_ops = { 118 .cpu_standby = k3_cpu_standby, 119 .pwr_domain_on = k3_pwr_domain_on, 120 .pwr_domain_off = k3_pwr_domain_off, 121 .pwr_domain_on_finish = k3_pwr_domain_on_finish, 122 .system_reset = k3_system_reset, 123 .validate_power_state = k3_validate_power_state, 124 .validate_ns_entrypoint = k3_validate_ns_entrypoint 125 }; 126 127 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 128 const plat_psci_ops_t **psci_ops) 129 { 130 k3_sec_entrypoint = sec_entrypoint; 131 132 *psci_ops = &k3_plat_psci_ops; 133 134 return 0; 135 } 136