1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/el3_runtime/cpu_data.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <k3_gicv3.h> 17 #include <ti_sci.h> 18 19 /* Need to flush psci internal locks before shutdown or their values are lost */ 20 #include "../../../../lib/psci/psci_private.h" 21 22 #define STUB() ERROR("stub %s called\n", __func__) 23 24 uintptr_t k3_sec_entrypoint; 25 26 static void k3_cpu_standby(plat_local_state_t cpu_state) 27 { 28 unsigned int scr; 29 30 scr = read_scr_el3(); 31 /* Enable the Non secure interrupt to wake the CPU */ 32 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 33 isb(); 34 /* dsb is good practice before using wfi to enter low power states */ 35 dsb(); 36 /* Enter standby state */ 37 wfi(); 38 /* Restore SCR */ 39 write_scr_el3(scr); 40 } 41 42 static int k3_pwr_domain_on(u_register_t mpidr) 43 { 44 int core_id, proc, device, ret; 45 46 core_id = plat_core_pos_by_mpidr(mpidr); 47 if (core_id < 0) { 48 ERROR("Could not get target core id: %d\n", core_id); 49 return PSCI_E_INTERN_FAIL; 50 } 51 52 proc = PLAT_PROC_START_ID + core_id; 53 device = PLAT_PROC_DEVICE_START_ID + core_id; 54 55 ret = ti_sci_proc_request(proc); 56 if (ret) { 57 ERROR("Request for processor failed: %d\n", ret); 58 return PSCI_E_INTERN_FAIL; 59 } 60 61 ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0); 62 if (ret) { 63 ERROR("Request to set core boot address failed: %d\n", ret); 64 return PSCI_E_INTERN_FAIL; 65 } 66 67 ret = ti_sci_device_get(device); 68 if (ret) { 69 ERROR("Request to start core failed: %d\n", ret); 70 return PSCI_E_INTERN_FAIL; 71 } 72 73 ret = ti_sci_proc_release(proc); 74 if (ret) { 75 /* this is not fatal */ 76 WARN("Could not release processor control: %d\n", ret); 77 } 78 79 return PSCI_E_SUCCESS; 80 } 81 82 void k3_pwr_domain_off(const psci_power_state_t *target_state) 83 { 84 int core_id, proc, device, ret; 85 86 /* Prevent interrupts from spuriously waking up this cpu */ 87 k3_gic_cpuif_disable(); 88 89 core_id = plat_my_core_pos(); 90 proc = PLAT_PROC_START_ID + core_id; 91 device = PLAT_PROC_DEVICE_START_ID + core_id; 92 93 ret = ti_sci_proc_shutdown(proc, device); 94 if (ret) { 95 ERROR("Request to stop core failed: %d\n", ret); 96 return; 97 } 98 } 99 100 void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) 101 { 102 /* TODO: Indicate to System firmware about completion */ 103 104 k3_gic_pcpu_init(); 105 k3_gic_cpuif_enable(); 106 } 107 108 static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t 109 *target_state) 110 { 111 flush_cpu_data(psci_svc_cpu_data); 112 flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks)); 113 psci_power_down_wfi(); 114 } 115 116 static void __dead2 k3_system_reset(void) 117 { 118 /* Send the system reset request to system firmware */ 119 ti_sci_core_reboot(); 120 121 while (true) 122 wfi(); 123 } 124 125 static int k3_validate_power_state(unsigned int power_state, 126 psci_power_state_t *req_state) 127 { 128 /* TODO: perform the proper validation */ 129 130 return PSCI_E_SUCCESS; 131 } 132 133 static int k3_validate_ns_entrypoint(uintptr_t entrypoint) 134 { 135 /* TODO: perform the proper validation */ 136 137 return PSCI_E_SUCCESS; 138 } 139 140 static const plat_psci_ops_t k3_plat_psci_ops = { 141 .cpu_standby = k3_cpu_standby, 142 .pwr_domain_on = k3_pwr_domain_on, 143 .pwr_domain_off = k3_pwr_domain_off, 144 .pwr_domain_on_finish = k3_pwr_domain_on_finish, 145 .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi, 146 .system_reset = k3_system_reset, 147 .validate_power_state = k3_validate_power_state, 148 .validate_ns_entrypoint = k3_validate_ns_entrypoint 149 }; 150 151 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 152 const plat_psci_ops_t **psci_ops) 153 { 154 k3_sec_entrypoint = sec_entrypoint; 155 156 *psci_ops = &k3_plat_psci_ops; 157 158 return 0; 159 } 160