1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cpu_data.h> 10 #include <debug.h> 11 #include <k3_gicv3.h> 12 #include <psci.h> 13 /* Need to flush psci internal locks before shutdown or their values are lost */ 14 #include <../../lib/psci/psci_private.h> 15 #include <platform.h> 16 #include <stdbool.h> 17 18 #include <ti_sci.h> 19 20 #define STUB() ERROR("stub %s called\n", __func__) 21 22 uintptr_t k3_sec_entrypoint; 23 24 static void k3_cpu_standby(plat_local_state_t cpu_state) 25 { 26 unsigned int scr; 27 28 scr = read_scr_el3(); 29 /* Enable the Non secure interrupt to wake the CPU */ 30 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 31 isb(); 32 /* dsb is good practice before using wfi to enter low power states */ 33 dsb(); 34 /* Enter standby state */ 35 wfi(); 36 /* Restore SCR */ 37 write_scr_el3(scr); 38 } 39 40 static int k3_pwr_domain_on(u_register_t mpidr) 41 { 42 int core_id, proc, device, ret; 43 44 core_id = plat_core_pos_by_mpidr(mpidr); 45 if (core_id < 0) { 46 ERROR("Could not get target core id: %d\n", core_id); 47 return PSCI_E_INTERN_FAIL; 48 } 49 50 proc = PLAT_PROC_START_ID + core_id; 51 device = PLAT_PROC_DEVICE_START_ID + core_id; 52 53 ret = ti_sci_proc_request(proc); 54 if (ret) { 55 ERROR("Request for processor failed: %d\n", ret); 56 return PSCI_E_INTERN_FAIL; 57 } 58 59 ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0); 60 if (ret) { 61 ERROR("Request to set core boot address failed: %d\n", ret); 62 return PSCI_E_INTERN_FAIL; 63 } 64 65 ret = ti_sci_device_get(device); 66 if (ret) { 67 ERROR("Request to start core failed: %d\n", ret); 68 return PSCI_E_INTERN_FAIL; 69 } 70 71 ret = ti_sci_proc_release(proc); 72 if (ret) { 73 /* this is not fatal */ 74 WARN("Could not release processor control: %d\n", ret); 75 } 76 77 return PSCI_E_SUCCESS; 78 } 79 80 void k3_pwr_domain_off(const psci_power_state_t *target_state) 81 { 82 int core_id, device, ret; 83 84 /* Prevent interrupts from spuriously waking up this cpu */ 85 k3_gic_cpuif_disable(); 86 87 core_id = plat_my_core_pos(); 88 device = PLAT_PROC_DEVICE_START_ID + core_id; 89 90 ret = ti_sci_device_put(device); 91 if (ret) { 92 ERROR("Request to stop core failed: %d\n", ret); 93 return; 94 } 95 } 96 97 void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) 98 { 99 /* TODO: Indicate to System firmware about completion */ 100 101 k3_gic_pcpu_init(); 102 k3_gic_cpuif_enable(); 103 } 104 105 static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t 106 *target_state) 107 { 108 flush_cpu_data(psci_svc_cpu_data); 109 flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks)); 110 psci_power_down_wfi(); 111 } 112 113 static void __dead2 k3_system_reset(void) 114 { 115 /* Send the system reset request to system firmware */ 116 ti_sci_core_reboot(); 117 118 while (true) 119 wfi(); 120 } 121 122 static int k3_validate_power_state(unsigned int power_state, 123 psci_power_state_t *req_state) 124 { 125 /* TODO: perform the proper validation */ 126 127 return PSCI_E_SUCCESS; 128 } 129 130 static int k3_validate_ns_entrypoint(uintptr_t entrypoint) 131 { 132 /* TODO: perform the proper validation */ 133 134 return PSCI_E_SUCCESS; 135 } 136 137 static const plat_psci_ops_t k3_plat_psci_ops = { 138 .cpu_standby = k3_cpu_standby, 139 .pwr_domain_on = k3_pwr_domain_on, 140 .pwr_domain_off = k3_pwr_domain_off, 141 .pwr_domain_on_finish = k3_pwr_domain_on_finish, 142 .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi, 143 .system_reset = k3_system_reset, 144 .validate_power_state = k3_validate_power_state, 145 .validate_ns_entrypoint = k3_validate_ns_entrypoint 146 }; 147 148 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 149 const plat_psci_ops_t **psci_ops) 150 { 151 k3_sec_entrypoint = sec_entrypoint; 152 153 *psci_ops = &k3_plat_psci_ops; 154 155 return 0; 156 } 157