1 /* 2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 19 #include <k3_console.h> 20 #include <k3_gicv3.h> 21 #include <ti_sci.h> 22 23 #define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U)) 24 #define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr)) 25 26 #define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \ 27 MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr) 28 29 /* Table of regions to map using the MMU */ 30 const mmap_region_t plat_k3_mmap[] = { 31 K3_MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 32 K3_MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 33 K3_MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 34 K3_MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 35 K3_MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 36 K3_MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 37 { /* sentinel */ } 38 }; 39 40 /* 41 * Placeholder variables for maintaining information about the next image(s) 42 */ 43 static entry_point_info_t bl32_image_ep_info; 44 static entry_point_info_t bl33_image_ep_info; 45 46 /******************************************************************************* 47 * Gets SPSR for BL33 entry 48 ******************************************************************************/ 49 static uint32_t k3_get_spsr_for_bl33_entry(void) 50 { 51 unsigned long el_status; 52 unsigned int mode; 53 uint32_t spsr; 54 55 /* Figure out what mode we enter the non-secure world in */ 56 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 57 el_status &= ID_AA64PFR0_ELX_MASK; 58 59 mode = (el_status) ? MODE_EL2 : MODE_EL1; 60 61 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 62 return spsr; 63 } 64 65 /******************************************************************************* 66 * Perform any BL3-1 early platform setup, such as console init and deciding on 67 * memory layout. 68 ******************************************************************************/ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 /* Initialize the console to provide early debug support */ 73 k3_console_setup(); 74 75 #ifdef BL32_BASE 76 /* Populate entry point information for BL32 */ 77 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 78 bl32_image_ep_info.pc = BL32_BASE; 79 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 80 DISABLE_ALL_EXCEPTIONS); 81 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 82 #endif 83 84 /* Populate entry point information for BL33 */ 85 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 86 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 87 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry(); 88 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 89 90 #ifdef K3_HW_CONFIG_BASE 91 /* 92 * According to the file ``Documentation/arm64/booting.txt`` of the 93 * Linux kernel tree, Linux expects the physical address of the device 94 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 95 * must be 0. 96 */ 97 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE; 98 bl33_image_ep_info.args.arg1 = 0U; 99 bl33_image_ep_info.args.arg2 = 0U; 100 bl33_image_ep_info.args.arg3 = 0U; 101 #endif 102 } 103 104 void bl31_plat_arch_setup(void) 105 { 106 const mmap_region_t bl_regions[] = { 107 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE), 108 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE), 109 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE), 110 #if USE_COHERENT_MEM 111 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), 112 #endif 113 { /* sentinel */ } 114 }; 115 116 setup_page_tables(bl_regions, plat_k3_mmap); 117 enable_mmu_el3(0); 118 } 119 120 void bl31_platform_setup(void) 121 { 122 struct ti_sci_msg_version version; 123 int ret; 124 125 k3_gic_driver_init(K3_GIC_BASE); 126 k3_gic_init(); 127 128 ret = ti_sci_get_revision(&version); 129 if (ret) { 130 ERROR("Unable to communicate with the control firmware (%d)\n", ret); 131 return; 132 } 133 134 INFO("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n", 135 version.abi_major, version.abi_minor, 136 version.firmware_revision, 137 version.firmware_description); 138 139 /* 140 * Older firmware have a timing issue with DM that crashes few TF-A 141 * lite devices while trying to make calls to DM. Since there is no way 142 * to detect what current DM version we are running - we rely on the 143 * corresponding TIFS versioning to handle this check and ensure that 144 * the platform boots up 145 * 146 * Upgrading to TIFS version 9.1.7 along with the corresponding DM from 147 * ti-linux-firmware will enable this functionality. 148 */ 149 if (version.firmware_revision > 9 || 150 (version.firmware_revision == 9 && version.sub_version > 1) || 151 (version.firmware_revision == 9 && version.sub_version == 1 && 152 version.patch_version >= 7) 153 ) { 154 if (ti_sci_device_get(PLAT_BOARD_DEVICE_ID)) { 155 WARN("Unable to take system power reference\n"); 156 } 157 } else { 158 NOTICE("Upgrade Firmwares for Power off functionality\n"); 159 } 160 } 161 162 void platform_mem_init(void) 163 { 164 /* Do nothing for now... */ 165 } 166 167 unsigned int plat_get_syscnt_freq2(void) 168 { 169 uint32_t gtc_freq; 170 uint32_t gtc_ctrl; 171 172 /* Lets try and provide basic diagnostics - cost is low */ 173 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET); 174 /* Did the bootloader fail to enable timer and OS guys are confused? */ 175 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) { 176 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n"); 177 } 178 /* 179 * If debug will not pause time, we will have issues like 180 * drivers timing out while debugging, in cases of OS like Linux, 181 * RCU stall errors, which can be hard to differentiate vs real issues. 182 */ 183 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) { 184 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n"); 185 } 186 187 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET); 188 /* Many older bootloaders may have missed programming FID0 register */ 189 if (gtc_freq != 0U) { 190 return gtc_freq; 191 } 192 193 /* 194 * We could have just warned about this, but this can have serious 195 * hard to debug side effects if we are NOT sure what the actual 196 * frequency is. Lets make sure people don't miss this. 197 */ 198 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n", 199 SYS_COUNTER_FREQ_IN_TICKS); 200 201 return SYS_COUNTER_FREQ_IN_TICKS; 202 } 203 204 /******************************************************************************* 205 * Return a pointer to the 'entry_point_info' structure of the next image 206 * for the security state specified. BL3-3 corresponds to the non-secure 207 * image type while BL3-2 corresponds to the secure image type. A NULL 208 * pointer is returned if the image does not exist. 209 ******************************************************************************/ 210 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 211 { 212 entry_point_info_t *next_image_info; 213 214 assert(sec_state_is_valid(type)); 215 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info : 216 &bl32_image_ep_info; 217 /* 218 * None of the images on the ARM development platforms can have 0x0 219 * as the entrypoint 220 */ 221 if (next_image_info->pc) 222 return next_image_info; 223 224 NOTICE("Requested nonexistent image\n"); 225 return NULL; 226 } 227