1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 19 #include <k3_console.h> 20 #include <k3_gicv3.h> 21 #include <ti_sci.h> 22 23 /* Table of regions to map using the MMU */ 24 const mmap_region_t plat_k3_mmap[] = { 25 MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 26 MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 28 MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 31 { /* sentinel */ } 32 }; 33 34 /* 35 * Placeholder variables for maintaining information about the next image(s) 36 */ 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 /******************************************************************************* 41 * Gets SPSR for BL33 entry 42 ******************************************************************************/ 43 static uint32_t k3_get_spsr_for_bl33_entry(void) 44 { 45 unsigned long el_status; 46 unsigned int mode; 47 uint32_t spsr; 48 49 /* Figure out what mode we enter the non-secure world in */ 50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 51 el_status &= ID_AA64PFR0_ELX_MASK; 52 53 mode = (el_status) ? MODE_EL2 : MODE_EL1; 54 55 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 56 return spsr; 57 } 58 59 /******************************************************************************* 60 * Perform any BL3-1 early platform setup, such as console init and deciding on 61 * memory layout. 62 ******************************************************************************/ 63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 64 u_register_t arg2, u_register_t arg3) 65 { 66 /* There are no parameters from BL2 if BL31 is a reset vector */ 67 assert(arg0 == 0U); 68 assert(arg1 == 0U); 69 70 /* Initialize the console to provide early debug support */ 71 k3_console_setup(); 72 73 #ifdef BL32_BASE 74 /* Populate entry point information for BL32 */ 75 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 76 bl32_image_ep_info.pc = BL32_BASE; 77 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 78 DISABLE_ALL_EXCEPTIONS); 79 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 80 #endif 81 82 /* Populate entry point information for BL33 */ 83 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 84 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 85 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry(); 86 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 87 88 #ifdef K3_HW_CONFIG_BASE 89 /* 90 * According to the file ``Documentation/arm64/booting.txt`` of the 91 * Linux kernel tree, Linux expects the physical address of the device 92 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 93 * must be 0. 94 */ 95 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE; 96 bl33_image_ep_info.args.arg1 = 0U; 97 bl33_image_ep_info.args.arg2 = 0U; 98 bl33_image_ep_info.args.arg3 = 0U; 99 #endif 100 } 101 102 void bl31_plat_arch_setup(void) 103 { 104 const mmap_region_t bl_regions[] = { 105 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE), 106 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE), 107 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE), 108 #if USE_COHERENT_MEM 109 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), 110 #endif 111 { /* sentinel */ } 112 }; 113 114 setup_page_tables(bl_regions, plat_k3_mmap); 115 enable_mmu_el3(0); 116 } 117 118 void bl31_platform_setup(void) 119 { 120 k3_gic_driver_init(K3_GIC_BASE); 121 k3_gic_init(); 122 123 ti_sci_init(); 124 } 125 126 void platform_mem_init(void) 127 { 128 /* Do nothing for now... */ 129 } 130 131 unsigned int plat_get_syscnt_freq2(void) 132 { 133 uint32_t gtc_freq; 134 uint32_t gtc_ctrl; 135 136 /* Lets try and provide basic diagnostics - cost is low */ 137 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET); 138 /* Did the bootloader fail to enable timer and OS guys are confused? */ 139 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) { 140 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n"); 141 } 142 /* 143 * If debug will not pause time, we will have issues like 144 * drivers timing out while debugging, in cases of OS like Linux, 145 * RCU stall errors, which can be hard to differentiate vs real issues. 146 */ 147 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) { 148 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n"); 149 } 150 151 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET); 152 /* Many older bootloaders may have missed programming FID0 register */ 153 if (gtc_freq != 0U) { 154 return gtc_freq; 155 } 156 157 /* 158 * We could have just warned about this, but this can have serious 159 * hard to debug side effects if we are NOT sure what the actual 160 * frequency is. Lets make sure people don't miss this. 161 */ 162 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n", 163 SYS_COUNTER_FREQ_IN_TICKS); 164 165 return SYS_COUNTER_FREQ_IN_TICKS; 166 } 167 168 /******************************************************************************* 169 * Return a pointer to the 'entry_point_info' structure of the next image 170 * for the security state specified. BL3-3 corresponds to the non-secure 171 * image type while BL3-2 corresponds to the secure image type. A NULL 172 * pointer is returned if the image does not exist. 173 ******************************************************************************/ 174 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 175 { 176 entry_point_info_t *next_image_info; 177 178 assert(sec_state_is_valid(type)); 179 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info : 180 &bl32_image_ep_info; 181 /* 182 * None of the images on the ARM development platforms can have 0x0 183 * as the entrypoint 184 */ 185 if (next_image_info->pc) 186 return next_image_info; 187 188 NOTICE("Requested nonexistent image\n"); 189 return NULL; 190 } 191