xref: /rk3399_ARM-atf/plat/ti/k3/common/k3_bl31_setup.c (revision e9cb89cfca8dad4d84e59a28932483fb3ddf8504)
11841c533SNishanth Menon /*
21841c533SNishanth Menon  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
31841c533SNishanth Menon  *
41841c533SNishanth Menon  * SPDX-License-Identifier: BSD-3-Clause
51841c533SNishanth Menon  */
61841c533SNishanth Menon 
71841c533SNishanth Menon #include <arch.h>
81841c533SNishanth Menon #include <arch_helpers.h>
91841c533SNishanth Menon #include <assert.h>
101841c533SNishanth Menon #include <bl_common.h>
111841c533SNishanth Menon #include <debug.h>
12fff6ffcaSNishanth Menon #include <k3_console.h>
13e67bfcf3SNishanth Menon #include <plat_arm.h>
141841c533SNishanth Menon #include <platform_def.h>
151841c533SNishanth Menon #include <string.h>
161841c533SNishanth Menon 
17e67bfcf3SNishanth Menon /* Table of regions to map using the MMU */
18e67bfcf3SNishanth Menon const mmap_region_t plat_arm_mmap[] = {
19e67bfcf3SNishanth Menon 	MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
20fff6ffcaSNishanth Menon 	MAP_REGION_FLAT(K3_USART_BASE_ADDRESS, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
21e67bfcf3SNishanth Menon 	{ /* sentinel */ }
22e67bfcf3SNishanth Menon };
23e67bfcf3SNishanth Menon 
24a546d25bSBenjamin Fair /*
25a546d25bSBenjamin Fair  * Placeholder variables for maintaining information about the next image(s)
26a546d25bSBenjamin Fair  */
27a546d25bSBenjamin Fair static entry_point_info_t bl32_image_ep_info;
28a546d25bSBenjamin Fair static entry_point_info_t bl33_image_ep_info;
29a546d25bSBenjamin Fair 
30a546d25bSBenjamin Fair /*******************************************************************************
31a546d25bSBenjamin Fair  * Gets SPSR for BL33 entry
32a546d25bSBenjamin Fair  ******************************************************************************/
33a546d25bSBenjamin Fair static uint32_t k3_get_spsr_for_bl33_entry(void)
34a546d25bSBenjamin Fair {
35a546d25bSBenjamin Fair 	unsigned long el_status;
36a546d25bSBenjamin Fair 	unsigned int mode;
37a546d25bSBenjamin Fair 	uint32_t spsr;
38a546d25bSBenjamin Fair 
39a546d25bSBenjamin Fair 	/* Figure out what mode we enter the non-secure world in */
40a546d25bSBenjamin Fair 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
41a546d25bSBenjamin Fair 	el_status &= ID_AA64PFR0_ELX_MASK;
42a546d25bSBenjamin Fair 
43a546d25bSBenjamin Fair 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
44a546d25bSBenjamin Fair 
45a546d25bSBenjamin Fair 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
46a546d25bSBenjamin Fair 	return spsr;
47a546d25bSBenjamin Fair }
48a546d25bSBenjamin Fair 
491841c533SNishanth Menon /*******************************************************************************
501841c533SNishanth Menon  * Perform any BL3-1 early platform setup, such as console init and deciding on
511841c533SNishanth Menon  * memory layout.
521841c533SNishanth Menon  ******************************************************************************/
531841c533SNishanth Menon void bl31_early_platform_setup(bl31_params_t *from_bl2,
541841c533SNishanth Menon 			       void *plat_params_from_bl2)
551841c533SNishanth Menon {
561841c533SNishanth Menon 	/* There are no parameters from BL2 if BL31 is a reset vector */
571841c533SNishanth Menon 	assert(from_bl2 == NULL);
581841c533SNishanth Menon 	assert(plat_params_from_bl2 == NULL);
59a546d25bSBenjamin Fair 
60fff6ffcaSNishanth Menon 	bl31_console_setup();
61fff6ffcaSNishanth Menon 
62a546d25bSBenjamin Fair #ifdef BL32_BASE
63a546d25bSBenjamin Fair 	/* Populate entry point information for BL32 */
64a546d25bSBenjamin Fair 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
65a546d25bSBenjamin Fair 	bl32_image_ep_info.pc = BL32_BASE;
66a546d25bSBenjamin Fair 	bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
67a546d25bSBenjamin Fair 					  DISABLE_ALL_EXCEPTIONS);
68a546d25bSBenjamin Fair 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
69a546d25bSBenjamin Fair #endif
70a546d25bSBenjamin Fair 
71a546d25bSBenjamin Fair 	/* Populate entry point information for BL33 */
72a546d25bSBenjamin Fair 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
73a546d25bSBenjamin Fair 	bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
74a546d25bSBenjamin Fair 	bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
75a546d25bSBenjamin Fair 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
76a546d25bSBenjamin Fair 
77a546d25bSBenjamin Fair #ifdef K3_HW_CONFIG_BASE
78a546d25bSBenjamin Fair 	/*
79a546d25bSBenjamin Fair 	 * According to the file ``Documentation/arm64/booting.txt`` of the
80a546d25bSBenjamin Fair 	 * Linux kernel tree, Linux expects the physical address of the device
81a546d25bSBenjamin Fair 	 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
82a546d25bSBenjamin Fair 	 * must be 0.
83a546d25bSBenjamin Fair 	 */
84a546d25bSBenjamin Fair 	bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
85a546d25bSBenjamin Fair 	bl33_image_ep_info.args.arg1 = 0U;
86a546d25bSBenjamin Fair 	bl33_image_ep_info.args.arg2 = 0U;
87a546d25bSBenjamin Fair 	bl33_image_ep_info.args.arg3 = 0U;
88a546d25bSBenjamin Fair #endif
891841c533SNishanth Menon }
901841c533SNishanth Menon 
911841c533SNishanth Menon void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
921841c533SNishanth Menon 				u_register_t arg2, u_register_t arg3)
931841c533SNishanth Menon {
941841c533SNishanth Menon 	bl31_early_platform_setup((void *)arg0, (void *)arg1);
951841c533SNishanth Menon }
961841c533SNishanth Menon 
971841c533SNishanth Menon void bl31_plat_arch_setup(void)
981841c533SNishanth Menon {
99e67bfcf3SNishanth Menon 	arm_setup_page_tables(BL31_BASE,
100e67bfcf3SNishanth Menon 			      BL31_END - BL31_BASE,
101e67bfcf3SNishanth Menon 			      BL_CODE_BASE,
102e67bfcf3SNishanth Menon 			      BL_CODE_END,
103e67bfcf3SNishanth Menon 			      BL_RO_DATA_BASE,
104e67bfcf3SNishanth Menon 			      BL_RO_DATA_END);
105e67bfcf3SNishanth Menon 	enable_mmu_el3(0);
1061841c533SNishanth Menon }
1071841c533SNishanth Menon 
1081841c533SNishanth Menon void bl31_platform_setup(void)
1091841c533SNishanth Menon {
1101841c533SNishanth Menon 	/* TODO: Initialize the GIC CPU and distributor interfaces */
1111841c533SNishanth Menon }
1121841c533SNishanth Menon 
1131841c533SNishanth Menon void platform_mem_init(void)
1141841c533SNishanth Menon {
1151841c533SNishanth Menon 	/* Do nothing for now... */
1161841c533SNishanth Menon }
1171841c533SNishanth Menon 
118*e9cb89cfSNishanth Menon unsigned int plat_get_syscnt_freq2(void)
119*e9cb89cfSNishanth Menon {
120*e9cb89cfSNishanth Menon 	return SYS_COUNTER_FREQ_IN_TICKS;
121*e9cb89cfSNishanth Menon }
122*e9cb89cfSNishanth Menon 
1231841c533SNishanth Menon /*
1241841c533SNishanth Menon  * Empty function to prevent the console from being uninitialized after BL33 is
1251841c533SNishanth Menon  * started and allow us to see messages from BL31.
1261841c533SNishanth Menon  */
1271841c533SNishanth Menon void bl31_plat_runtime_setup(void)
1281841c533SNishanth Menon {
1291841c533SNishanth Menon }
1301841c533SNishanth Menon 
1311841c533SNishanth Menon /*******************************************************************************
1321841c533SNishanth Menon  * Return a pointer to the 'entry_point_info' structure of the next image
1331841c533SNishanth Menon  * for the security state specified. BL3-3 corresponds to the non-secure
1341841c533SNishanth Menon  * image type while BL3-2 corresponds to the secure image type. A NULL
1351841c533SNishanth Menon  * pointer is returned if the image does not exist.
1361841c533SNishanth Menon  ******************************************************************************/
1371841c533SNishanth Menon entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
1381841c533SNishanth Menon {
139a546d25bSBenjamin Fair 	entry_point_info_t *next_image_info;
140a546d25bSBenjamin Fair 
141a546d25bSBenjamin Fair 	assert(sec_state_is_valid(type));
142a546d25bSBenjamin Fair 	next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
143a546d25bSBenjamin Fair 						 &bl32_image_ep_info;
144a546d25bSBenjamin Fair 	/*
145a546d25bSBenjamin Fair 	 * None of the images on the ARM development platforms can have 0x0
146a546d25bSBenjamin Fair 	 * as the entrypoint
147a546d25bSBenjamin Fair 	 */
148a546d25bSBenjamin Fair 	if (next_image_info->pc)
149a546d25bSBenjamin Fair 		return next_image_info;
150a546d25bSBenjamin Fair 
151a546d25bSBenjamin Fair 	NOTICE("Requested nonexistent image\n");
1521841c533SNishanth Menon 	return NULL;
1531841c533SNishanth Menon }
154