14a566b26SHari Nagalla# 24a566b26SHari Nagalla# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 34a566b26SHari Nagalla# 44a566b26SHari Nagalla# SPDX-License-Identifier: BSD-3-Clause 54a566b26SHari Nagalla# 64a566b26SHari Nagalla 74a566b26SHari NagallaBL32_BASE ?= 0x9e800000 84a566b26SHari Nagalla$(eval $(call add_define,BL32_BASE)) 94a566b26SHari Nagalla 104a566b26SHari NagallaPRELOADED_BL33_BASE ?= 0x80080000 114a566b26SHari Nagalla$(eval $(call add_define,PRELOADED_BL33_BASE)) 124a566b26SHari Nagalla 134a566b26SHari NagallaK3_HW_CONFIG_BASE ?= 0x82000000 144a566b26SHari Nagalla$(eval $(call add_define,K3_HW_CONFIG_BASE)) 154a566b26SHari Nagalla 164a566b26SHari Nagalla# Define sec_proxy usage as the full prioritized communication scheme 174a566b26SHari NagallaK3_SEC_PROXY_LITE := 0 184a566b26SHari Nagalla$(eval $(call add_define,K3_SEC_PROXY_LITE)) 194a566b26SHari Nagalla 20*aee2f33aSAndrew Davis# Use a 4 cycle data RAM latency for J784s4 21*aee2f33aSAndrew DavisK3_DATA_RAM_4_LATENCY := 1 22*aee2f33aSAndrew Davis$(eval $(call add_define,K3_DATA_RAM_4_LATENCY)) 23*aee2f33aSAndrew Davis 244a566b26SHari Nagalla# System coherency is managed in hardware 254a566b26SHari NagallaUSE_COHERENT_MEM := 1 264a566b26SHari Nagalla 274a566b26SHari NagallaPLAT_INCLUDES += \ 284a566b26SHari Nagalla -Iplat/ti/k3/board/j784s4/include \ 29