1 /* 2 * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <ti_sci.h> 17 18 #include <k3_console.h> 19 #include <k3_gicv3.h> 20 #include <plat_private.h> 21 #include <platform_def.h> 22 23 /* 24 * Placeholder variables for maintaining information about the next image(s) 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 /******************************************************************************* 30 * Gets SPSR for BL33 entry 31 ******************************************************************************/ 32 static uint32_t k3_get_spsr_for_bl33_entry(void) 33 { 34 unsigned long el_status; 35 unsigned int mode; 36 uint32_t spsr; 37 38 /* Figure out what mode we enter the non-secure world in */ 39 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 40 el_status &= ID_AA64PFR0_ELX_MASK; 41 42 mode = (el_status) ? MODE_EL2 : MODE_EL1; 43 44 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 45 return spsr; 46 } 47 48 /******************************************************************************* 49 * Perform any BL3-1 early platform setup, such as console init and deciding on 50 * memory layout. 51 ******************************************************************************/ 52 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 53 u_register_t arg2, u_register_t arg3) 54 { 55 /* Initialize the console to provide early debug support */ 56 k3_console_setup(); 57 58 #ifdef BL32_BASE 59 /* Populate entry point information for BL32 */ 60 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 61 bl32_image_ep_info.pc = BL32_BASE; 62 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 63 DISABLE_ALL_EXCEPTIONS); 64 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 65 #endif 66 67 /* Populate entry point information for BL33 */ 68 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 69 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 70 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry(); 71 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 72 73 #ifdef K3_HW_CONFIG_BASE 74 /* 75 * According to the file ``Documentation/arch/arm64/booting.rst`` of the 76 * Linux kernel tree, Linux expects the physical address of the device 77 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 78 * must be 0. 79 */ 80 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE; 81 bl33_image_ep_info.args.arg1 = 0U; 82 bl33_image_ep_info.args.arg2 = 0U; 83 bl33_image_ep_info.args.arg3 = 0U; 84 #endif 85 } 86 87 void bl31_plat_arch_setup(void) 88 { 89 const mmap_region_t bl_regions[] = { 90 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 92 MT_CODE | MT_RO | MT_SECURE), 93 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 94 MT_RO_DATA | MT_RO | MT_SECURE), 95 #if USE_COHERENT_MEM 96 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 97 MT_DEVICE | MT_RW | MT_SECURE), 98 #endif 99 { /* sentinel */ } 100 }; 101 102 setup_page_tables(bl_regions, plat_k3_mmap); 103 enable_mmu_el3(0); 104 } 105 106 void bl31_platform_setup(void) 107 { 108 k3_gic_driver_init(K3_GIC_BASE); 109 k3_gic_init(); 110 ti_soc_init(); 111 } 112 113 void platform_mem_init(void) 114 { 115 /* Do nothing for now... */ 116 } 117 118 unsigned int plat_get_syscnt_freq2(void) 119 { 120 uint32_t gtc_freq; 121 uint32_t gtc_ctrl; 122 123 /* Lets try and provide basic diagnostics - cost is low */ 124 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET); 125 /* Did the bootloader fail to enable timer and OS guys are confused? */ 126 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) { 127 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n"); 128 } 129 /* 130 * If debug will not pause time, we will have issues like 131 * drivers timing out while debugging, in cases of OS like Linux, 132 * RCU stall errors, which can be hard to differentiate vs real issues. 133 */ 134 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) { 135 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n"); 136 } 137 138 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET); 139 /* Many older bootloaders may have missed programming FID0 register */ 140 if (gtc_freq != 0U) { 141 return gtc_freq; 142 } 143 144 /* 145 * We could have just warned about this, but this can have serious 146 * hard to debug side effects if we are NOT sure what the actual 147 * frequency is. Lets make sure people don't miss this. 148 */ 149 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n", 150 SYS_COUNTER_FREQ_IN_TICKS); 151 152 return SYS_COUNTER_FREQ_IN_TICKS; 153 } 154 155 /******************************************************************************* 156 * Return a pointer to the 'entry_point_info' structure of the next image 157 * for the security state specified. BL3-3 corresponds to the non-secure 158 * image type while BL3-2 corresponds to the secure image type. A NULL 159 * pointer is returned if the image does not exist. 160 ******************************************************************************/ 161 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 162 { 163 entry_point_info_t *next_image_info; 164 165 assert(sec_state_is_valid(type)); 166 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info : 167 &bl32_image_ep_info; 168 /* 169 * None of the images on the ARM development platforms can have 0x0 170 * as the entrypoint 171 */ 172 if (next_image_info->pc) 173 return next_image_info; 174 175 NOTICE("Requested nonexistent image\n"); 176 return NULL; 177 } 178