1*bfac44b5SDhruva Gole# 2*bfac44b5SDhruva Gole# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3*bfac44b5SDhruva Gole# 4*bfac44b5SDhruva Gole# SPDX-License-Identifier: BSD-3-Clause 5*bfac44b5SDhruva Gole# 6*bfac44b5SDhruva Gole 7*bfac44b5SDhruva Gole# We don't use BL1 or BL2, so BL31 is the first image to execute 8*bfac44b5SDhruva GoleRESET_TO_BL31 := 1 9*bfac44b5SDhruva Gole# Only one core starts up at first 10*bfac44b5SDhruva GoleCOLD_BOOT_SINGLE_CPU := 1 11*bfac44b5SDhruva Gole# We can choose where a core starts executing 12*bfac44b5SDhruva GolePROGRAMMABLE_RESET_ADDRESS:= 1 13*bfac44b5SDhruva Gole 14*bfac44b5SDhruva Gole# ARM coherency is managed in hardware 15*bfac44b5SDhruva GoleWARMBOOT_ENABLE_DCACHE_EARLY := 1 16*bfac44b5SDhruva Gole 17*bfac44b5SDhruva Gole# A53 erratum for SoC. (enable them all) 18*bfac44b5SDhruva GoleERRATA_A53_826319 := 1 19*bfac44b5SDhruva GoleERRATA_A53_835769 := 1 20*bfac44b5SDhruva GoleERRATA_A53_836870 := 1 21*bfac44b5SDhruva GoleERRATA_A53_843419 := 1 22*bfac44b5SDhruva GoleERRATA_A53_855873 := 1 23*bfac44b5SDhruva GoleERRATA_A53_1530924 := 1 24*bfac44b5SDhruva Gole 25*bfac44b5SDhruva Gole# A72 Erratum for SoC 26*bfac44b5SDhruva GoleERRATA_A72_859971 := 1 27*bfac44b5SDhruva GoleERRATA_A72_1319367 := 1 28*bfac44b5SDhruva Gole 29*bfac44b5SDhruva GoleCRASH_REPORTING := 1 30*bfac44b5SDhruva Gole 31*bfac44b5SDhruva Gole# Split out RO data into a non-executable section 32*bfac44b5SDhruva GoleSEPARATE_CODE_AND_RODATA := 1 33*bfac44b5SDhruva Gole 34*bfac44b5SDhruva Gole# Generate a Position Independent Executable 35*bfac44b5SDhruva GoleENABLE_PIE := 1 36*bfac44b5SDhruva Gole 37*bfac44b5SDhruva GoleTI_16550_MDR_QUIRK := 1 38*bfac44b5SDhruva Gole$(eval $(call add_define,TI_16550_MDR_QUIRK)) 39*bfac44b5SDhruva Gole 40*bfac44b5SDhruva GoleK3_USART := 0 41*bfac44b5SDhruva Gole$(eval $(call add_define,K3_USART)) 42*bfac44b5SDhruva Gole 43*bfac44b5SDhruva Gole# Allow customizing the UART baud rate 44*bfac44b5SDhruva GoleK3_USART_BAUD := 115200 45*bfac44b5SDhruva Gole$(eval $(call add_define,K3_USART_BAUD)) 46*bfac44b5SDhruva Gole 47*bfac44b5SDhruva Gole# Libraries 48*bfac44b5SDhruva Goleinclude lib/xlat_tables_v2/xlat_tables.mk 49*bfac44b5SDhruva Gole 50*bfac44b5SDhruva GolePLAT_INCLUDES += \ 51*bfac44b5SDhruva Gole -I${PLAT_PATH}/include \ 52*bfac44b5SDhruva Gole -Idrivers/ti/ti_sci \ 53*bfac44b5SDhruva Gole 54*bfac44b5SDhruva GoleK3_CONSOLE_SOURCES += \ 55*bfac44b5SDhruva Gole drivers/ti/uart/aarch64/16550_console.S \ 56*bfac44b5SDhruva Gole plat/ti/common/k3_console.c \ 57*bfac44b5SDhruva Gole 58*bfac44b5SDhruva Gole# Include GICv3 driver files 59*bfac44b5SDhruva Goleinclude drivers/arm/gic/v3/gicv3.mk 60*bfac44b5SDhruva Gole 61*bfac44b5SDhruva GoleK3_GIC_SOURCES += \ 62*bfac44b5SDhruva Gole ${GICV3_SOURCES} \ 63*bfac44b5SDhruva Gole plat/common/plat_gicv3.c \ 64*bfac44b5SDhruva Gole plat/ti/common/k3_gicv3.c \ 65*bfac44b5SDhruva Gole 66*bfac44b5SDhruva GoleK3_PSCI_SOURCES += \ 67*bfac44b5SDhruva Gole plat/common/plat_psci_common.c \ 68*bfac44b5SDhruva Gole 69*bfac44b5SDhruva Gole 70*bfac44b5SDhruva GoleK3_TI_SCI_SOURCES += \ 71*bfac44b5SDhruva Gole drivers/ti/ti_sci/ti_sci.c \ 72*bfac44b5SDhruva Gole 73*bfac44b5SDhruva GolePLAT_BL_COMMON_SOURCES += \ 74*bfac44b5SDhruva Gole lib/cpus/aarch64/cortex_a53.S \ 75*bfac44b5SDhruva Gole lib/cpus/aarch64/cortex_a72.S \ 76*bfac44b5SDhruva Gole ${XLAT_TABLES_LIB_SRCS} \ 77*bfac44b5SDhruva Gole ${K3_CONSOLE_SOURCES} \ 78*bfac44b5SDhruva Gole 79*bfac44b5SDhruva GoleBL31_SOURCES += \ 80*bfac44b5SDhruva Gole plat/ti/common/ti_bl31_setup.c \ 81*bfac44b5SDhruva Gole plat/ti/common/k3_helpers.S \ 82*bfac44b5SDhruva Gole ${K3_GIC_SOURCES} \ 83*bfac44b5SDhruva Gole ${K3_TI_SCI_SOURCES} \ 84