1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 11 #include <platform_def.h> 12 13 #define BKPR_BOOT_MODE 96U 14 15 #if defined(IMAGE_BL31) 16 /* BL31 only uses the first half of the SYSRAM */ 17 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 18 STM32MP_SYSRAM_SIZE / 2U, \ 19 MT_MEMORY | \ 20 MT_RW | \ 21 MT_SECURE | \ 22 MT_EXECUTE_NEVER) 23 #else 24 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 25 STM32MP_SYSRAM_SIZE, \ 26 MT_MEMORY | \ 27 MT_RW | \ 28 MT_SECURE | \ 29 MT_EXECUTE_NEVER) 30 #endif 31 32 #if STM32MP_DDR_FIP_IO_STORAGE 33 #define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \ 34 SRAM1_SIZE_FOR_TFA, \ 35 MT_MEMORY | \ 36 MT_RW | \ 37 MT_SECURE | \ 38 MT_EXECUTE_NEVER) 39 #endif 40 41 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 42 STM32MP_DEVICE_SIZE, \ 43 MT_DEVICE | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 #if defined(IMAGE_BL2) 49 static const mmap_region_t stm32mp2_mmap[] = { 50 MAP_SYSRAM, 51 #if STM32MP_DDR_FIP_IO_STORAGE 52 MAP_SRAM1, 53 #endif 54 MAP_DEVICE, 55 {0} 56 }; 57 #endif 58 #if defined(IMAGE_BL31) 59 static const mmap_region_t stm32mp2_mmap[] = { 60 MAP_SYSRAM, 61 MAP_DEVICE, 62 {0} 63 }; 64 #endif 65 66 void configure_mmu(void) 67 { 68 mmap_add(stm32mp2_mmap); 69 init_xlat_tables(); 70 71 enable_mmu_el3(0); 72 } 73 74 int stm32mp_map_retram(void) 75 { 76 return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE, 77 RETRAM_SIZE, 78 MT_RW | MT_SECURE); 79 } 80 81 int stm32mp_unmap_retram(void) 82 { 83 return mmap_remove_dynamic_region(RETRAM_BASE, 84 RETRAM_SIZE); 85 } 86 87 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 88 { 89 if (bank == GPIO_BANK_Z) { 90 return GPIOZ_BASE; 91 } 92 93 assert(bank <= GPIO_BANK_K); 94 95 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 96 } 97 98 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 99 { 100 if (bank == GPIO_BANK_Z) { 101 return 0; 102 } 103 104 assert(bank <= GPIO_BANK_K); 105 106 return bank * GPIO_BANK_OFFSET; 107 } 108 109 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 110 { 111 if (bank == GPIO_BANK_Z) { 112 return CK_BUS_GPIOZ; 113 } 114 115 assert(bank <= GPIO_BANK_K); 116 117 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 118 } 119 120 uint32_t stm32mp_get_chip_version(void) 121 { 122 static uint32_t rev; 123 124 if (rev != 0U) { 125 return rev; 126 } 127 128 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 129 panic(); 130 } 131 132 return rev; 133 } 134 135 uint32_t stm32mp_get_chip_dev_id(void) 136 { 137 return stm32mp_syscfg_get_chip_dev_id(); 138 } 139 140 static uint32_t get_part_number(void) 141 { 142 static uint32_t part_number; 143 144 if (part_number != 0U) { 145 return part_number; 146 } 147 148 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 149 panic(); 150 } 151 152 return part_number; 153 } 154 155 static uint32_t get_cpu_package(void) 156 { 157 static uint32_t package = UINT32_MAX; 158 159 if (package == UINT32_MAX) { 160 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 161 panic(); 162 } 163 } 164 165 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 166 } 167 168 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 169 { 170 char *cpu_s, *cpu_r, *pkg; 171 172 /* MPUs Part Numbers */ 173 switch (get_part_number()) { 174 case STM32MP251A_PART_NB: 175 cpu_s = "251A"; 176 break; 177 case STM32MP251C_PART_NB: 178 cpu_s = "251C"; 179 break; 180 case STM32MP251D_PART_NB: 181 cpu_s = "251D"; 182 break; 183 case STM32MP251F_PART_NB: 184 cpu_s = "251F"; 185 break; 186 case STM32MP253A_PART_NB: 187 cpu_s = "253A"; 188 break; 189 case STM32MP253C_PART_NB: 190 cpu_s = "253C"; 191 break; 192 case STM32MP253D_PART_NB: 193 cpu_s = "253D"; 194 break; 195 case STM32MP253F_PART_NB: 196 cpu_s = "253F"; 197 break; 198 case STM32MP255A_PART_NB: 199 cpu_s = "255A"; 200 break; 201 case STM32MP255C_PART_NB: 202 cpu_s = "255C"; 203 break; 204 case STM32MP255D_PART_NB: 205 cpu_s = "255D"; 206 break; 207 case STM32MP255F_PART_NB: 208 cpu_s = "255F"; 209 break; 210 case STM32MP257A_PART_NB: 211 cpu_s = "257A"; 212 break; 213 case STM32MP257C_PART_NB: 214 cpu_s = "257C"; 215 break; 216 case STM32MP257D_PART_NB: 217 cpu_s = "257D"; 218 break; 219 case STM32MP257F_PART_NB: 220 cpu_s = "257F"; 221 break; 222 default: 223 cpu_s = "????"; 224 break; 225 } 226 227 /* Package */ 228 switch (get_cpu_package()) { 229 case STM32MP25_PKG_CUSTOM: 230 pkg = "XX"; 231 break; 232 case STM32MP25_PKG_AL_VFBGA361: 233 pkg = "AL"; 234 break; 235 case STM32MP25_PKG_AK_VFBGA424: 236 pkg = "AK"; 237 break; 238 case STM32MP25_PKG_AI_TFBGA436: 239 pkg = "AI"; 240 break; 241 default: 242 pkg = "??"; 243 break; 244 } 245 246 /* REVISION */ 247 switch (stm32mp_get_chip_version()) { 248 case STM32MP2_REV_A: 249 cpu_r = "A"; 250 break; 251 case STM32MP2_REV_B: 252 cpu_r = "B"; 253 break; 254 case STM32MP2_REV_X: 255 cpu_r = "X"; 256 break; 257 case STM32MP2_REV_Y: 258 cpu_r = "Y"; 259 break; 260 case STM32MP2_REV_Z: 261 cpu_r = "Z"; 262 break; 263 default: 264 cpu_r = "?"; 265 break; 266 } 267 268 snprintf(name, STM32_SOC_NAME_SIZE, 269 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 270 } 271 272 void stm32mp_print_cpuinfo(void) 273 { 274 char name[STM32_SOC_NAME_SIZE]; 275 276 stm32mp_get_soc_name(name); 277 NOTICE("CPU: %s\n", name); 278 } 279 280 void stm32mp_print_boardinfo(void) 281 { 282 uint32_t board_id = 0U; 283 284 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 285 return; 286 } 287 288 if (board_id != 0U) { 289 stm32_display_board_info(board_id); 290 } 291 } 292 293 bool stm32mp_is_wakeup_from_standby(void) 294 { 295 /* TODO add source code to determine if platform is waking up from standby mode */ 296 return false; 297 } 298 299 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 300 { 301 return tamp_bkpr(BKPR_BOOT_MODE); 302 } 303 304 uintptr_t stm32_ddrdbg_get_base(void) 305 { 306 return DDRDBG_BASE; 307 } 308