1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 12 #include <platform_def.h> 13 14 #define BKPR_FWU_INFO 48U 15 #define BKPR_BOOT_MODE 96U 16 17 #if defined(IMAGE_BL31) 18 /* BL31 only uses the first half of the SYSRAM */ 19 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 20 STM32MP_SYSRAM_SIZE / 2U, \ 21 MT_MEMORY | \ 22 MT_RW | \ 23 MT_SECURE | \ 24 MT_EXECUTE_NEVER) 25 #else 26 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 27 STM32MP_SYSRAM_SIZE, \ 28 MT_MEMORY | \ 29 MT_RW | \ 30 MT_SECURE | \ 31 MT_EXECUTE_NEVER) 32 #endif 33 34 #if STM32MP_USB_PROGRAMMER 35 #define MAP_SYSRAM_MEM MAP_REGION_FLAT(STM32MP_SYSRAM_MEM_BASE, \ 36 STM32MP_SYSRAM_MEM_SIZE, \ 37 MT_MEMORY | \ 38 MT_RW | \ 39 MT_SECURE | \ 40 MT_EXECUTE_NEVER) 41 42 #define MAP_SYSRAM_DEV MAP_REGION_FLAT(STM32MP_SYSRAM_DEVICE_BASE, \ 43 STM32MP_SYSRAM_DEVICE_SIZE, \ 44 MT_DEVICE | \ 45 MT_RW | \ 46 MT_SECURE | \ 47 MT_EXECUTE_NEVER) 48 #endif 49 50 #if STM32MP_DDR_FIP_IO_STORAGE 51 #define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \ 52 SRAM1_SIZE_FOR_TFA, \ 53 MT_MEMORY | \ 54 MT_RW | \ 55 MT_SECURE | \ 56 MT_EXECUTE_NEVER) 57 #endif 58 59 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 60 STM32MP_DEVICE_SIZE, \ 61 MT_DEVICE | \ 62 MT_RW | \ 63 MT_SECURE | \ 64 MT_EXECUTE_NEVER) 65 66 #if defined(IMAGE_BL2) 67 static const mmap_region_t stm32mp2_mmap[] = { 68 #if STM32MP_USB_PROGRAMMER 69 MAP_SYSRAM_MEM, 70 MAP_SYSRAM_DEV, 71 #else 72 MAP_SYSRAM, 73 #endif 74 #if STM32MP_DDR_FIP_IO_STORAGE 75 MAP_SRAM1, 76 #endif 77 MAP_DEVICE, 78 {0} 79 }; 80 #endif 81 #if defined(IMAGE_BL31) 82 static const mmap_region_t stm32mp2_mmap[] = { 83 MAP_SYSRAM, 84 MAP_DEVICE, 85 {0} 86 }; 87 #endif 88 89 void configure_mmu(void) 90 { 91 mmap_add(stm32mp2_mmap); 92 init_xlat_tables(); 93 94 enable_mmu_el3(0); 95 } 96 97 int stm32mp_map_retram(void) 98 { 99 return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE, 100 RETRAM_SIZE, 101 MT_RW | MT_SECURE); 102 } 103 104 int stm32mp_unmap_retram(void) 105 { 106 return mmap_remove_dynamic_region(RETRAM_BASE, 107 RETRAM_SIZE); 108 } 109 110 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 111 { 112 if (bank == GPIO_BANK_Z) { 113 return GPIOZ_BASE; 114 } 115 116 assert(bank <= GPIO_BANK_K); 117 118 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 119 } 120 121 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 122 { 123 if (bank == GPIO_BANK_Z) { 124 return 0; 125 } 126 127 assert(bank <= GPIO_BANK_K); 128 129 return bank * GPIO_BANK_OFFSET; 130 } 131 132 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 133 { 134 if (bank == GPIO_BANK_Z) { 135 return CK_BUS_GPIOZ; 136 } 137 138 assert(bank <= GPIO_BANK_K); 139 140 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 141 } 142 143 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 144 /* 145 * UART Management 146 */ 147 static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = { 148 USART1_BASE, 149 USART2_BASE, 150 USART3_BASE, 151 UART4_BASE, 152 UART5_BASE, 153 USART6_BASE, 154 UART7_BASE, 155 UART8_BASE, 156 UART9_BASE, 157 }; 158 159 uintptr_t get_uart_address(uint32_t instance_nb) 160 { 161 if ((instance_nb == 0U) || 162 (instance_nb > STM32MP_NB_OF_UART)) { 163 return 0U; 164 } 165 166 return stm32mp2_uart_addresses[instance_nb - 1U]; 167 } 168 #endif 169 170 uint32_t stm32mp_get_chip_version(void) 171 { 172 static uint32_t rev; 173 174 if (rev != 0U) { 175 return rev; 176 } 177 178 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 179 panic(); 180 } 181 182 return rev; 183 } 184 185 uint32_t stm32mp_get_chip_dev_id(void) 186 { 187 return stm32mp_syscfg_get_chip_dev_id(); 188 } 189 190 static uint32_t get_part_number(void) 191 { 192 static uint32_t part_number; 193 194 if (part_number != 0U) { 195 return part_number; 196 } 197 198 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 199 panic(); 200 } 201 202 return part_number; 203 } 204 205 static uint32_t get_cpu_package(void) 206 { 207 static uint32_t package = UINT32_MAX; 208 209 if (package == UINT32_MAX) { 210 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 211 panic(); 212 } 213 } 214 215 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 216 } 217 218 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 219 { 220 char *cpu_s, *cpu_r, *pkg; 221 222 /* MPUs Part Numbers */ 223 switch (get_part_number()) { 224 case STM32MP251A_PART_NB: 225 cpu_s = "251A"; 226 break; 227 case STM32MP251C_PART_NB: 228 cpu_s = "251C"; 229 break; 230 case STM32MP251D_PART_NB: 231 cpu_s = "251D"; 232 break; 233 case STM32MP251F_PART_NB: 234 cpu_s = "251F"; 235 break; 236 case STM32MP253A_PART_NB: 237 cpu_s = "253A"; 238 break; 239 case STM32MP253C_PART_NB: 240 cpu_s = "253C"; 241 break; 242 case STM32MP253D_PART_NB: 243 cpu_s = "253D"; 244 break; 245 case STM32MP253F_PART_NB: 246 cpu_s = "253F"; 247 break; 248 case STM32MP255A_PART_NB: 249 cpu_s = "255A"; 250 break; 251 case STM32MP255C_PART_NB: 252 cpu_s = "255C"; 253 break; 254 case STM32MP255D_PART_NB: 255 cpu_s = "255D"; 256 break; 257 case STM32MP255F_PART_NB: 258 cpu_s = "255F"; 259 break; 260 case STM32MP257A_PART_NB: 261 cpu_s = "257A"; 262 break; 263 case STM32MP257C_PART_NB: 264 cpu_s = "257C"; 265 break; 266 case STM32MP257D_PART_NB: 267 cpu_s = "257D"; 268 break; 269 case STM32MP257F_PART_NB: 270 cpu_s = "257F"; 271 break; 272 default: 273 cpu_s = "????"; 274 break; 275 } 276 277 /* Package */ 278 switch (get_cpu_package()) { 279 case STM32MP25_PKG_CUSTOM: 280 pkg = "XX"; 281 break; 282 case STM32MP25_PKG_AL_VFBGA361: 283 pkg = "AL"; 284 break; 285 case STM32MP25_PKG_AK_VFBGA424: 286 pkg = "AK"; 287 break; 288 case STM32MP25_PKG_AI_TFBGA436: 289 pkg = "AI"; 290 break; 291 default: 292 pkg = "??"; 293 break; 294 } 295 296 /* REVISION */ 297 switch (stm32mp_get_chip_version()) { 298 case STM32MP2_REV_A: 299 cpu_r = "A"; 300 break; 301 case STM32MP2_REV_B: 302 cpu_r = "B"; 303 break; 304 case STM32MP2_REV_X: 305 cpu_r = "X"; 306 break; 307 case STM32MP2_REV_Y: 308 cpu_r = "Y"; 309 break; 310 case STM32MP2_REV_Z: 311 cpu_r = "Z"; 312 break; 313 default: 314 cpu_r = "?"; 315 break; 316 } 317 318 snprintf(name, STM32_SOC_NAME_SIZE, 319 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 320 } 321 322 void stm32mp_print_cpuinfo(void) 323 { 324 char name[STM32_SOC_NAME_SIZE]; 325 326 stm32mp_get_soc_name(name); 327 NOTICE("CPU: %s\n", name); 328 } 329 330 void stm32mp_print_boardinfo(void) 331 { 332 uint32_t board_id = 0U; 333 334 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 335 return; 336 } 337 338 if (board_id != 0U) { 339 stm32_display_board_info(board_id); 340 } 341 } 342 343 /* Return true when SoC provides a single Cortex-A35 core, and false otherwise */ 344 bool stm32mp_is_single_core(void) 345 { 346 bool single_core = false; 347 348 switch (get_part_number()) { 349 case STM32MP251A_PART_NB: 350 case STM32MP251C_PART_NB: 351 case STM32MP251D_PART_NB: 352 case STM32MP251F_PART_NB: 353 single_core = true; 354 break; 355 default: 356 break; 357 } 358 359 return single_core; 360 } 361 362 /* Return true when device is in closed state */ 363 uint32_t stm32mp_check_closed_device(void) 364 { 365 return STM32MP_CHIP_SEC_OPEN; 366 } 367 368 /* Return true when device supports secure boot */ 369 bool stm32mp_is_auth_supported(void) 370 { 371 bool supported = false; 372 373 switch (get_part_number()) { 374 case STM32MP251C_PART_NB: 375 case STM32MP251F_PART_NB: 376 case STM32MP253C_PART_NB: 377 case STM32MP253F_PART_NB: 378 case STM32MP255C_PART_NB: 379 case STM32MP255F_PART_NB: 380 case STM32MP257C_PART_NB: 381 case STM32MP257F_PART_NB: 382 supported = true; 383 break; 384 default: 385 break; 386 } 387 388 return supported; 389 } 390 391 bool stm32mp_is_wakeup_from_standby(void) 392 { 393 /* TODO add source code to determine if platform is waking up from standby mode */ 394 return false; 395 } 396 397 int stm32_risaf_get_instance(uintptr_t base) 398 { 399 switch (base) { 400 case RISAF2_BASE: 401 return (int)RISAF2_INST; 402 case RISAF4_BASE: 403 return (int)RISAF4_INST; 404 default: 405 return -ENODEV; 406 } 407 } 408 409 uintptr_t stm32_risaf_get_base(int instance) 410 { 411 switch (instance) { 412 case RISAF2_INST: 413 return (uintptr_t)RISAF2_BASE; 414 case RISAF4_INST: 415 return (uintptr_t)RISAF4_BASE; 416 default: 417 return 0U; 418 } 419 } 420 421 int stm32_risaf_get_max_region(int instance) 422 { 423 switch (instance) { 424 case RISAF2_INST: 425 return (int)RISAF2_MAX_REGION; 426 case RISAF4_INST: 427 return (int)RISAF4_MAX_REGION; 428 default: 429 return 0; 430 } 431 } 432 433 uintptr_t stm32_risaf_get_memory_base(int instance) 434 { 435 switch (instance) { 436 case RISAF2_INST: 437 return (uintptr_t)STM32MP_OSPI_MM_BASE; 438 case RISAF4_INST: 439 return (uintptr_t)STM32MP_DDR_BASE; 440 default: 441 return 0U; 442 } 443 } 444 445 size_t stm32_risaf_get_memory_size(int instance) 446 { 447 switch (instance) { 448 case RISAF2_INST: 449 return STM32MP_OSPI_MM_SIZE; 450 case RISAF4_INST: 451 return dt_get_ddr_size(); 452 default: 453 return 0U; 454 } 455 } 456 457 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 458 { 459 return tamp_bkpr(BKPR_BOOT_MODE); 460 } 461 462 #if PSA_FWU_SUPPORT 463 uintptr_t stm32_get_bkpr_fwu_info_addr(void) 464 { 465 return tamp_bkpr(BKPR_FWU_INFO); 466 } 467 #endif /* PSA_FWU_SUPPORT */ 468 469 uintptr_t stm32_ddrdbg_get_base(void) 470 { 471 return DDRDBG_BASE; 472 } 473