1db77f8bfSYann Gautier /* 2db77f8bfSYann Gautier * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3db77f8bfSYann Gautier * 4db77f8bfSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5db77f8bfSYann Gautier */ 6db77f8bfSYann Gautier 7db77f8bfSYann Gautier #include <assert.h> 8db77f8bfSYann Gautier 9db77f8bfSYann Gautier #include <lib/xlat_tables/xlat_tables_v2.h> 10db77f8bfSYann Gautier 11db77f8bfSYann Gautier #include <platform_def.h> 12db77f8bfSYann Gautier 13db77f8bfSYann Gautier #define BKPR_BOOT_MODE 96U 14db77f8bfSYann Gautier 15db77f8bfSYann Gautier #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 16db77f8bfSYann Gautier STM32MP_SYSRAM_SIZE, \ 17db77f8bfSYann Gautier MT_MEMORY | \ 18db77f8bfSYann Gautier MT_RW | \ 19db77f8bfSYann Gautier MT_SECURE | \ 20db77f8bfSYann Gautier MT_EXECUTE_NEVER) 21db77f8bfSYann Gautier 22db77f8bfSYann Gautier #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 23db77f8bfSYann Gautier STM32MP_DEVICE_SIZE, \ 24db77f8bfSYann Gautier MT_DEVICE | \ 25db77f8bfSYann Gautier MT_RW | \ 26db77f8bfSYann Gautier MT_SECURE | \ 27db77f8bfSYann Gautier MT_EXECUTE_NEVER) 28db77f8bfSYann Gautier 29db77f8bfSYann Gautier #if defined(IMAGE_BL2) 30db77f8bfSYann Gautier static const mmap_region_t stm32mp2_mmap[] = { 31db77f8bfSYann Gautier MAP_SYSRAM, 32db77f8bfSYann Gautier MAP_DEVICE, 33db77f8bfSYann Gautier {0} 34db77f8bfSYann Gautier }; 35db77f8bfSYann Gautier #endif 36db77f8bfSYann Gautier 37db77f8bfSYann Gautier void configure_mmu(void) 38db77f8bfSYann Gautier { 39db77f8bfSYann Gautier mmap_add(stm32mp2_mmap); 40db77f8bfSYann Gautier init_xlat_tables(); 41db77f8bfSYann Gautier 42db77f8bfSYann Gautier enable_mmu_el3(0); 43db77f8bfSYann Gautier } 44db77f8bfSYann Gautier 45db77f8bfSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 46db77f8bfSYann Gautier { 47db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 48db77f8bfSYann Gautier return GPIOZ_BASE; 49db77f8bfSYann Gautier } 50db77f8bfSYann Gautier 51db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 52db77f8bfSYann Gautier 53db77f8bfSYann Gautier return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 54db77f8bfSYann Gautier } 55db77f8bfSYann Gautier 56db77f8bfSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 57db77f8bfSYann Gautier { 58db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 59db77f8bfSYann Gautier return 0; 60db77f8bfSYann Gautier } 61db77f8bfSYann Gautier 62db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 63db77f8bfSYann Gautier 64db77f8bfSYann Gautier return bank * GPIO_BANK_OFFSET; 65db77f8bfSYann Gautier } 66db77f8bfSYann Gautier 67db77f8bfSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 68db77f8bfSYann Gautier { 69db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 70db77f8bfSYann Gautier return CK_BUS_GPIOZ; 71db77f8bfSYann Gautier } 72db77f8bfSYann Gautier 73db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 74db77f8bfSYann Gautier 75db77f8bfSYann Gautier return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 76db77f8bfSYann Gautier } 77db77f8bfSYann Gautier 78*381b2a6bSYann Gautier uint32_t stm32mp_get_chip_version(void) 79*381b2a6bSYann Gautier { 80*381b2a6bSYann Gautier static uint32_t rev; 81*381b2a6bSYann Gautier 82*381b2a6bSYann Gautier if (rev != 0U) { 83*381b2a6bSYann Gautier return rev; 84*381b2a6bSYann Gautier } 85*381b2a6bSYann Gautier 86*381b2a6bSYann Gautier if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 87*381b2a6bSYann Gautier panic(); 88*381b2a6bSYann Gautier } 89*381b2a6bSYann Gautier 90*381b2a6bSYann Gautier return rev; 91*381b2a6bSYann Gautier } 92*381b2a6bSYann Gautier 93*381b2a6bSYann Gautier uint32_t stm32mp_get_chip_dev_id(void) 94*381b2a6bSYann Gautier { 95*381b2a6bSYann Gautier return stm32mp_syscfg_get_chip_dev_id(); 96*381b2a6bSYann Gautier } 97*381b2a6bSYann Gautier 98*381b2a6bSYann Gautier static uint32_t get_part_number(void) 99*381b2a6bSYann Gautier { 100*381b2a6bSYann Gautier static uint32_t part_number; 101*381b2a6bSYann Gautier 102*381b2a6bSYann Gautier if (part_number != 0U) { 103*381b2a6bSYann Gautier return part_number; 104*381b2a6bSYann Gautier } 105*381b2a6bSYann Gautier 106*381b2a6bSYann Gautier if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 107*381b2a6bSYann Gautier panic(); 108*381b2a6bSYann Gautier } 109*381b2a6bSYann Gautier 110*381b2a6bSYann Gautier return part_number; 111*381b2a6bSYann Gautier } 112*381b2a6bSYann Gautier 113*381b2a6bSYann Gautier static uint32_t get_cpu_package(void) 114*381b2a6bSYann Gautier { 115*381b2a6bSYann Gautier static uint32_t package = UINT32_MAX; 116*381b2a6bSYann Gautier 117*381b2a6bSYann Gautier if (package == UINT32_MAX) { 118*381b2a6bSYann Gautier if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 119*381b2a6bSYann Gautier panic(); 120*381b2a6bSYann Gautier } 121*381b2a6bSYann Gautier } 122*381b2a6bSYann Gautier 123*381b2a6bSYann Gautier return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 124*381b2a6bSYann Gautier } 125*381b2a6bSYann Gautier 126*381b2a6bSYann Gautier void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 127*381b2a6bSYann Gautier { 128*381b2a6bSYann Gautier char *cpu_s, *cpu_r, *pkg; 129*381b2a6bSYann Gautier 130*381b2a6bSYann Gautier /* MPUs Part Numbers */ 131*381b2a6bSYann Gautier switch (get_part_number()) { 132*381b2a6bSYann Gautier case STM32MP251A_PART_NB: 133*381b2a6bSYann Gautier cpu_s = "251A"; 134*381b2a6bSYann Gautier break; 135*381b2a6bSYann Gautier case STM32MP251C_PART_NB: 136*381b2a6bSYann Gautier cpu_s = "251C"; 137*381b2a6bSYann Gautier break; 138*381b2a6bSYann Gautier case STM32MP251D_PART_NB: 139*381b2a6bSYann Gautier cpu_s = "251D"; 140*381b2a6bSYann Gautier break; 141*381b2a6bSYann Gautier case STM32MP251F_PART_NB: 142*381b2a6bSYann Gautier cpu_s = "251F"; 143*381b2a6bSYann Gautier break; 144*381b2a6bSYann Gautier case STM32MP253A_PART_NB: 145*381b2a6bSYann Gautier cpu_s = "253A"; 146*381b2a6bSYann Gautier break; 147*381b2a6bSYann Gautier case STM32MP253C_PART_NB: 148*381b2a6bSYann Gautier cpu_s = "253C"; 149*381b2a6bSYann Gautier break; 150*381b2a6bSYann Gautier case STM32MP253D_PART_NB: 151*381b2a6bSYann Gautier cpu_s = "253D"; 152*381b2a6bSYann Gautier break; 153*381b2a6bSYann Gautier case STM32MP253F_PART_NB: 154*381b2a6bSYann Gautier cpu_s = "253F"; 155*381b2a6bSYann Gautier break; 156*381b2a6bSYann Gautier case STM32MP255A_PART_NB: 157*381b2a6bSYann Gautier cpu_s = "255A"; 158*381b2a6bSYann Gautier break; 159*381b2a6bSYann Gautier case STM32MP255C_PART_NB: 160*381b2a6bSYann Gautier cpu_s = "255C"; 161*381b2a6bSYann Gautier break; 162*381b2a6bSYann Gautier case STM32MP255D_PART_NB: 163*381b2a6bSYann Gautier cpu_s = "255D"; 164*381b2a6bSYann Gautier break; 165*381b2a6bSYann Gautier case STM32MP255F_PART_NB: 166*381b2a6bSYann Gautier cpu_s = "255F"; 167*381b2a6bSYann Gautier break; 168*381b2a6bSYann Gautier case STM32MP257A_PART_NB: 169*381b2a6bSYann Gautier cpu_s = "257A"; 170*381b2a6bSYann Gautier break; 171*381b2a6bSYann Gautier case STM32MP257C_PART_NB: 172*381b2a6bSYann Gautier cpu_s = "257C"; 173*381b2a6bSYann Gautier break; 174*381b2a6bSYann Gautier case STM32MP257D_PART_NB: 175*381b2a6bSYann Gautier cpu_s = "257D"; 176*381b2a6bSYann Gautier break; 177*381b2a6bSYann Gautier case STM32MP257F_PART_NB: 178*381b2a6bSYann Gautier cpu_s = "257F"; 179*381b2a6bSYann Gautier break; 180*381b2a6bSYann Gautier default: 181*381b2a6bSYann Gautier cpu_s = "????"; 182*381b2a6bSYann Gautier break; 183*381b2a6bSYann Gautier } 184*381b2a6bSYann Gautier 185*381b2a6bSYann Gautier /* Package */ 186*381b2a6bSYann Gautier switch (get_cpu_package()) { 187*381b2a6bSYann Gautier case STM32MP25_PKG_CUSTOM: 188*381b2a6bSYann Gautier pkg = "XX"; 189*381b2a6bSYann Gautier break; 190*381b2a6bSYann Gautier case STM32MP25_PKG_AL_VFBGA361: 191*381b2a6bSYann Gautier pkg = "AL"; 192*381b2a6bSYann Gautier break; 193*381b2a6bSYann Gautier case STM32MP25_PKG_AK_VFBGA424: 194*381b2a6bSYann Gautier pkg = "AK"; 195*381b2a6bSYann Gautier break; 196*381b2a6bSYann Gautier case STM32MP25_PKG_AI_TFBGA436: 197*381b2a6bSYann Gautier pkg = "AI"; 198*381b2a6bSYann Gautier break; 199*381b2a6bSYann Gautier default: 200*381b2a6bSYann Gautier pkg = "??"; 201*381b2a6bSYann Gautier break; 202*381b2a6bSYann Gautier } 203*381b2a6bSYann Gautier 204*381b2a6bSYann Gautier /* REVISION */ 205*381b2a6bSYann Gautier switch (stm32mp_get_chip_version()) { 206*381b2a6bSYann Gautier case STM32MP2_REV_A: 207*381b2a6bSYann Gautier cpu_r = "A"; 208*381b2a6bSYann Gautier break; 209*381b2a6bSYann Gautier case STM32MP2_REV_B: 210*381b2a6bSYann Gautier cpu_r = "B"; 211*381b2a6bSYann Gautier break; 212*381b2a6bSYann Gautier case STM32MP2_REV_X: 213*381b2a6bSYann Gautier cpu_r = "X"; 214*381b2a6bSYann Gautier break; 215*381b2a6bSYann Gautier case STM32MP2_REV_Y: 216*381b2a6bSYann Gautier cpu_r = "Y"; 217*381b2a6bSYann Gautier break; 218*381b2a6bSYann Gautier case STM32MP2_REV_Z: 219*381b2a6bSYann Gautier cpu_r = "Z"; 220*381b2a6bSYann Gautier break; 221*381b2a6bSYann Gautier default: 222*381b2a6bSYann Gautier cpu_r = "?"; 223*381b2a6bSYann Gautier break; 224*381b2a6bSYann Gautier } 225*381b2a6bSYann Gautier 226*381b2a6bSYann Gautier snprintf(name, STM32_SOC_NAME_SIZE, 227*381b2a6bSYann Gautier "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 228*381b2a6bSYann Gautier } 229*381b2a6bSYann Gautier 230*381b2a6bSYann Gautier void stm32mp_print_cpuinfo(void) 231*381b2a6bSYann Gautier { 232*381b2a6bSYann Gautier char name[STM32_SOC_NAME_SIZE]; 233*381b2a6bSYann Gautier 234*381b2a6bSYann Gautier stm32mp_get_soc_name(name); 235*381b2a6bSYann Gautier NOTICE("CPU: %s\n", name); 236*381b2a6bSYann Gautier } 237*381b2a6bSYann Gautier 238db77f8bfSYann Gautier uintptr_t stm32_get_bkpr_boot_mode_addr(void) 239db77f8bfSYann Gautier { 240db77f8bfSYann Gautier return tamp_bkpr(BKPR_BOOT_MODE); 241db77f8bfSYann Gautier } 242