1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #include <drivers/st/stm32mp2_clk.h> 14 #include <drivers/st/stm32mp2_risaf.h> 15 #endif 16 #if STM32MP21 17 #include <drivers/st/stm32mp21_pwr.h> 18 #include <drivers/st/stm32mp21_rcc.h> 19 #else /* STM32MP21 */ 20 #include <drivers/st/stm32mp2_pwr.h> 21 #include <drivers/st/stm32mp25_rcc.h> 22 #endif /* STM32MP21 */ 23 #if STM32MP21 24 #include <dt-bindings/clock/st,stm32mp21-rcc.h> 25 #include <dt-bindings/clock/stm32mp21-clksrc.h> 26 #include <dt-bindings/reset/st,stm32mp21-rcc.h> 27 #endif /* STM32MP21 */ 28 #if STM32MP23 29 #include <dt-bindings/clock/stm32mp25-clks.h> 30 #include <dt-bindings/clock/stm32mp25-clksrc.h> 31 #include <dt-bindings/reset/stm32mp25-resets.h> 32 #endif /* STM32MP23 */ 33 #if STM32MP25 34 #include <dt-bindings/clock/stm32mp25-clks.h> 35 #include <dt-bindings/clock/stm32mp25-clksrc.h> 36 #include <dt-bindings/reset/stm32mp25-resets.h> 37 #endif /* STM32MP25 */ 38 #include <dt-bindings/gpio/stm32-gpio.h> 39 #include <dt-bindings/soc/rif.h> 40 41 #ifndef __ASSEMBLER__ 42 #include <boot_api.h> 43 #include <stm32mp2_private.h> 44 #include <stm32mp_common.h> 45 #include <stm32mp_dt.h> 46 #include <stm32mp_shared_resources.h> 47 #endif 48 49 /******************************************************************************* 50 * CHIP ID 51 ******************************************************************************/ 52 #define STM32MP2_CHIP_ID U(0x505) 53 54 #define STM32MP251A_PART_NB U(0x400B3E6D) 55 #define STM32MP251C_PART_NB U(0x000B306D) 56 #define STM32MP251D_PART_NB U(0xC00B3E6D) 57 #define STM32MP251F_PART_NB U(0x800B306D) 58 #define STM32MP253A_PART_NB U(0x400B3E0C) 59 #define STM32MP253C_PART_NB U(0x000B300C) 60 #define STM32MP253D_PART_NB U(0xC00B3E0C) 61 #define STM32MP253F_PART_NB U(0x800B300C) 62 #define STM32MP255A_PART_NB U(0x40082E00) 63 #define STM32MP255C_PART_NB U(0x00082000) 64 #define STM32MP255D_PART_NB U(0xC0082E00) 65 #define STM32MP255F_PART_NB U(0x80082000) 66 #define STM32MP257A_PART_NB U(0x40002E00) 67 #define STM32MP257C_PART_NB U(0x00002000) 68 #define STM32MP257D_PART_NB U(0xC0002E00) 69 #define STM32MP257F_PART_NB U(0x80002000) 70 71 #define STM32MP2_REV_A U(0x08) 72 #define STM32MP2_REV_B U(0x10) 73 #define STM32MP2_REV_X U(0x12) 74 #define STM32MP2_REV_Y U(0x11) 75 #define STM32MP2_REV_Z U(0x09) 76 77 /******************************************************************************* 78 * PACKAGE ID 79 ******************************************************************************/ 80 #define STM32MP25_PKG_CUSTOM U(0) 81 #define STM32MP25_PKG_AL_VFBGA361 U(1) 82 #define STM32MP25_PKG_AK_VFBGA424 U(3) 83 #define STM32MP25_PKG_AI_TFBGA436 U(5) 84 #define STM32MP25_PKG_UNKNOWN U(7) 85 86 /******************************************************************************* 87 * STM32MP2 memory map related constants 88 ******************************************************************************/ 89 #define STM32MP_SYSRAM_BASE U(0x0E000000) 90 #define STM32MP_SYSRAM_SIZE U(0x00040000) 91 #define SRAM1_BASE U(0x0E040000) 92 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 93 #define RETRAM_BASE U(0x0E080000) 94 #define RETRAM_SIZE U(0x00020000) 95 96 /* DDR configuration */ 97 #define STM32MP_DDR_BASE U(0x80000000) 98 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 99 100 /* DDR power initializations */ 101 #ifndef __ASSEMBLER__ 102 enum ddr_type { 103 STM32MP_DDR3, 104 STM32MP_DDR4, 105 STM32MP_LPDDR4 106 }; 107 #endif 108 109 /* Section used inside TF binaries */ 110 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 111 /* 512 Bytes reserved for header */ 112 #define STM32MP_HEADER_SIZE U(0x00000200) 113 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 114 STM32MP_PARAM_LOAD_SIZE) 115 116 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 117 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 118 119 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 120 STM32MP_PARAM_LOAD_SIZE + \ 121 STM32MP_HEADER_SIZE) 122 123 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 124 (STM32MP_PARAM_LOAD_SIZE + \ 125 STM32MP_HEADER_SIZE)) 126 127 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 128 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 129 130 /* Allocate remaining sysram to BL31 Binary only */ 131 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 132 STM32MP_BL2_SIZE) 133 134 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 135 STM32MP_SYSRAM_SIZE - \ 136 STM32MP_BL2_SIZE) 137 138 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 139 140 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 141 STM32MP_BL2_RO_SIZE) 142 143 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 144 STM32MP_SYSRAM_SIZE - \ 145 STM32MP_BL2_RW_BASE) 146 147 /* BL2 and BL32/sp_min require 4 tables */ 148 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 149 150 /* 151 * MAX_MMAP_REGIONS is usually: 152 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 153 */ 154 #if defined(IMAGE_BL31) 155 #define MAX_MMAP_REGIONS 7 156 #else 157 #define MAX_MMAP_REGIONS 6 158 #endif 159 160 /* DTB initialization value */ 161 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 162 163 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 164 STM32MP_BL2_DTB_SIZE) 165 166 #if defined(IMAGE_BL2) 167 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 168 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 169 #endif 170 171 #if STM32MP_DDR_FIP_IO_STORAGE 172 #define STM32MP_DDR_FW_BASE SRAM1_BASE 173 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 174 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 175 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 176 #endif 177 178 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 179 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 180 181 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 182 #define STM32MP_BL33_MAX_SIZE U(0x400000) 183 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 184 STM32MP_BL33_MAX_SIZE) 185 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 186 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 187 188 /******************************************************************************* 189 * STM32MP2 device/io map related constants (used for MMU) 190 ******************************************************************************/ 191 #define STM32MP_DEVICE_BASE U(0x40000000) 192 #define STM32MP_DEVICE_SIZE U(0x40000000) 193 194 /******************************************************************************* 195 * STM32MP2 RCC 196 ******************************************************************************/ 197 #define RCC_BASE U(0x44200000) 198 199 /******************************************************************************* 200 * STM32MP2 PWR 201 ******************************************************************************/ 202 #define PWR_BASE U(0x44210000) 203 204 /******************************************************************************* 205 * STM32MP2 GPIO 206 ******************************************************************************/ 207 #define GPIOA_BASE U(0x44240000) 208 #define GPIOB_BASE U(0x44250000) 209 #define GPIOC_BASE U(0x44260000) 210 #define GPIOD_BASE U(0x44270000) 211 #define GPIOE_BASE U(0x44280000) 212 #define GPIOF_BASE U(0x44290000) 213 #define GPIOG_BASE U(0x442A0000) 214 #define GPIOH_BASE U(0x442B0000) 215 #define GPIOI_BASE U(0x442C0000) 216 #define GPIOJ_BASE U(0x442D0000) 217 #define GPIOK_BASE U(0x442E0000) 218 #define GPIOZ_BASE U(0x46200000) 219 #define GPIO_BANK_OFFSET U(0x10000) 220 221 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 222 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 223 224 /******************************************************************************* 225 * STM32MP2 UART 226 ******************************************************************************/ 227 #define USART1_BASE U(0x40330000) 228 #define USART2_BASE U(0x400E0000) 229 #define USART3_BASE U(0x400F0000) 230 #define UART4_BASE U(0x40100000) 231 #define UART5_BASE U(0x40110000) 232 #define USART6_BASE U(0x40220000) 233 #define UART7_BASE U(0x40370000) 234 #define UART8_BASE U(0x40380000) 235 #define UART9_BASE U(0x402C0000) 236 #define STM32MP_NB_OF_UART U(9) 237 238 /* For UART crash console */ 239 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 240 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 241 #ifdef ULTRA_FLY 242 #define STM32MP_DEBUG_USART_BASE USART1_BASE 243 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 244 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 245 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 246 #define DEBUG_UART_TX_GPIO_PORT 3 247 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 248 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 249 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 250 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 251 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 252 #define DEBUG_UART_RST_REG RCC_USART1CFGR 253 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 254 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 255 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 256 #else 257 #define STM32MP_DEBUG_USART_BASE USART2_BASE 258 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 259 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 260 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 261 #define DEBUG_UART_TX_GPIO_PORT 4 262 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 263 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 264 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 265 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 266 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 267 #define DEBUG_UART_RST_REG RCC_USART2CFGR 268 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 269 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 270 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 271 #endif 272 273 /******************************************************************************* 274 * STM32MP2 SDMMC 275 ******************************************************************************/ 276 #define STM32MP_SDMMC1_BASE U(0x48220000) 277 #define STM32MP_SDMMC2_BASE U(0x48230000) 278 #define STM32MP_SDMMC3_BASE U(0x48240000) 279 280 /******************************************************************************* 281 * STM32MP2 OSPI 282 ******************************************************************************/ 283 /* OSPI 1 & 2 memory map area */ 284 #define STM32MP_OSPI_MM_BASE U(0x60000000) 285 #define STM32MP_OSPI_MM_SIZE U(0x10000000) 286 287 /******************************************************************************* 288 * STM32MP2 BSEC / OTP 289 ******************************************************************************/ 290 /* 291 * 367 available OTPs, the other are masked 292 * - ECIES key: 368 to 375 (only readable by bootrom) 293 * - HWKEY: 376 to 383 (never reloadable or readable) 294 */ 295 #define STM32MP2_OTP_MAX_ID U(0x16F) 296 #define STM32MP2_MID_OTP_START U(0x80) 297 #define STM32MP2_UPPER_OTP_START U(0x100) 298 299 /* OTP labels */ 300 #define PART_NUMBER_OTP "part-number-otp" 301 #define REVISION_OTP "rev_otp" 302 #define PACKAGE_OTP "package-otp" 303 #define HCONF1_OTP "otp124" 304 #define NAND_OTP "otp16" 305 #define NAND2_OTP "otp20" 306 #define BOARD_ID_OTP "board-id" 307 #define UID_OTP "uid-otp" 308 #define LIFECYCLE2_OTP "otp18" 309 #define PKH_OTP "otp144" 310 #define ENCKEY_OTP "otp260" 311 312 /* OTP mask */ 313 /* PACKAGE */ 314 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 315 #define PACKAGE_OTP_PKG_SHIFT U(0) 316 317 /* IWDG OTP */ 318 #define HCONF1_OTP_IWDG_HW_POS U(0) 319 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 320 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 321 322 /* NAND OTP */ 323 /* NAND parameter storage flag */ 324 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 325 326 /* NAND page size in bytes */ 327 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 328 #define NAND_PAGE_SIZE_SHIFT U(29) 329 #define NAND_PAGE_SIZE_2K U(0) 330 #define NAND_PAGE_SIZE_4K U(1) 331 #define NAND_PAGE_SIZE_8K U(2) 332 333 /* NAND block size in pages */ 334 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 335 #define NAND_BLOCK_SIZE_SHIFT U(27) 336 #define NAND_BLOCK_SIZE_64_PAGES U(0) 337 #define NAND_BLOCK_SIZE_128_PAGES U(1) 338 #define NAND_BLOCK_SIZE_256_PAGES U(2) 339 340 /* NAND number of block (in unit of 256 blocks) */ 341 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 342 #define NAND_BLOCK_NB_SHIFT U(19) 343 #define NAND_BLOCK_NB_UNIT U(256) 344 345 /* NAND bus width in bits */ 346 #define NAND_WIDTH_MASK BIT_32(18) 347 #define NAND_WIDTH_SHIFT U(18) 348 349 /* NAND number of ECC bits per 512 bytes */ 350 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 351 #define NAND_ECC_BIT_NB_SHIFT U(15) 352 #define NAND_ECC_BIT_NB_UNSET U(0) 353 #define NAND_ECC_BIT_NB_1_BITS U(1) 354 #define NAND_ECC_BIT_NB_4_BITS U(2) 355 #define NAND_ECC_BIT_NB_8_BITS U(3) 356 #define NAND_ECC_ON_DIE U(4) 357 358 /* NAND number of planes */ 359 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 360 361 /* NAND2 OTP */ 362 #define NAND2_PAGE_SIZE_SHIFT U(16) 363 364 /* NAND2 config distribution */ 365 #define NAND2_CONFIG_DISTRIB BIT_32(0) 366 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 367 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 368 369 /* MONOTONIC OTP */ 370 #define MAX_MONOTONIC_VALUE U(32) 371 372 /* UID OTP */ 373 #define UID_WORD_NB U(3) 374 375 /* Lifecycle OTP */ 376 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 377 378 /******************************************************************************* 379 * STM32MP2 TAMP 380 ******************************************************************************/ 381 #define PLAT_MAX_TAMP_INT U(5) 382 #define PLAT_MAX_TAMP_EXT U(3) 383 #define TAMP_BASE U(0x46010000) 384 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 385 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 386 #define TAMP_BKP_REG_CLK CK_BUS_RTC 387 #define TAMP_BKP_SEC_NUMBER U(10) 388 #define TAMP_COUNTR U(0x40) 389 390 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 391 static inline uintptr_t tamp_bkpr(uint32_t idx) 392 { 393 return TAMP_BKP_REGISTER_BASE + (idx << 2); 394 } 395 #endif 396 397 /******************************************************************************* 398 * STM32MP2 DDRCTRL 399 ******************************************************************************/ 400 #define DDRCTRL_BASE U(0x48040000) 401 402 /******************************************************************************* 403 * STM32MP2 DDRDBG 404 ******************************************************************************/ 405 #define DDRDBG_BASE U(0x48050000) 406 407 /******************************************************************************* 408 * STM32MP2 DDRPHYC 409 ******************************************************************************/ 410 #define DDRPHYC_BASE U(0x48C00000) 411 412 /******************************************************************************* 413 * Miscellaneous STM32MP2 peripherals base address 414 ******************************************************************************/ 415 #define BSEC_BASE U(0x44000000) 416 #define DBGMCU_BASE U(0x4A010000) 417 #define HASH_BASE U(0x42010000) 418 #define RTC_BASE U(0x46000000) 419 #define STGEN_BASE U(0x48080000) 420 #define SYSCFG_BASE U(0x44230000) 421 422 /******************************************************************************* 423 * STM32MP RIF 424 ******************************************************************************/ 425 #define RISAB1_BASE U(0x420F0000) 426 #define RISAB2_BASE U(0x42100000) 427 #define RISAB3_BASE U(0x42110000) 428 #define RISAB5_BASE U(0x42130000) 429 430 #define RISAF1_INST 0 431 #define RISAF2_INST 1 432 #define RISAF4_INST 3 433 #define RISAF5_INST 4 434 #define RISAF_MAX_INSTANCE 5 435 436 #define RISAF1_BASE U(0x420A0000) 437 #define RISAF2_BASE U(0x420B0000) 438 #define RISAF4_BASE U(0x420D0000) 439 #define RISAF5_BASE U(0x420E0000) 440 441 #define USE_RISAF2 442 #define USE_RISAF4 443 444 #ifdef USE_RISAF1 445 #define RISAF1_MAX_REGION 4 446 #else 447 #define RISAF1_MAX_REGION 0 448 #endif 449 #ifdef USE_RISAF2 450 #define RISAF2_MAX_REGION 4 451 #else 452 #define RISAF2_MAX_REGION 0 453 #endif 454 #ifdef USE_RISAF4 455 /* Consider only encrypted region maximum number, to save memory consumption */ 456 #define RISAF4_MAX_REGION 4 457 #else 458 #define RISAF4_MAX_REGION 0 459 #endif 460 #ifdef USE_RISAF5 461 #define RISAF5_MAX_REGION 2 462 #else 463 #define RISAF5_MAX_REGION 0 464 #endif 465 #define RISAF_MAX_REGION (RISAF1_MAX_REGION + RISAF2_MAX_REGION + \ 466 RISAF4_MAX_REGION + RISAF5_MAX_REGION) 467 468 #define RISAF_KEY_SIZE_IN_BYTES RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES 469 #define RISAF_SEED_SIZE_IN_BYTES U(4) 470 471 /******************************************************************************* 472 * STM32MP CA35SSC 473 ******************************************************************************/ 474 #define A35SSC_BASE U(0x48800000) 475 476 /******************************************************************************* 477 * REGULATORS 478 ******************************************************************************/ 479 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 480 #define PLAT_NB_RDEVS U(19) 481 /* 2 FIXED */ 482 #define PLAT_NB_FIXED_REGUS U(2) 483 /* No GPIO regu */ 484 #define PLAT_NB_GPIO_REGUS U(0) 485 486 /******************************************************************************* 487 * Device Tree defines 488 ******************************************************************************/ 489 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 490 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 491 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 492 #if STM32MP21 493 #define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc" 494 #else 495 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 496 #endif 497 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 498 #define DT_UART_COMPAT "st,stm32h7-uart" 499 500 #endif /* STM32MP2_DEF_H */ 501