1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #include <dt-bindings/clock/stm32mp25-clks.h> 16 #include <dt-bindings/clock/stm32mp25-clksrc.h> 17 #include <dt-bindings/gpio/stm32-gpio.h> 18 #include <dt-bindings/reset/stm32mp25-resets.h> 19 20 #ifndef __ASSEMBLER__ 21 #include <boot_api.h> 22 #include <stm32mp2_private.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shared_resources.h> 26 #endif 27 28 /******************************************************************************* 29 * STM32MP2 memory map related constants 30 ******************************************************************************/ 31 #define STM32MP_SYSRAM_BASE U(0x0E000000) 32 #define STM32MP_SYSRAM_SIZE U(0x00040000) 33 34 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 35 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE 36 37 /* DDR configuration */ 38 #define STM32MP_DDR_BASE U(0x80000000) 39 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 40 41 /* DDR power initializations */ 42 #ifndef __ASSEMBLER__ 43 enum ddr_type { 44 STM32MP_DDR3, 45 STM32MP_DDR4, 46 STM32MP_LPDDR4 47 }; 48 #endif 49 50 /* Section used inside TF binaries */ 51 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 52 /* 512 Octets reserved for header */ 53 #define STM32MP_HEADER_SIZE U(0x00000200) 54 #define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \ 55 STM32MP_PARAM_LOAD_SIZE) 56 57 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 58 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 59 60 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 61 STM32MP_PARAM_LOAD_SIZE + \ 62 STM32MP_HEADER_SIZE) 63 64 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 65 (STM32MP_PARAM_LOAD_SIZE + \ 66 STM32MP_HEADER_SIZE)) 67 68 #define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */ 69 70 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 71 STM32MP_SEC_SYSRAM_SIZE - \ 72 STM32MP_BL2_SIZE) 73 74 /* BL2 and BL32/sp_min require 4 tables */ 75 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 76 77 /* 78 * MAX_MMAP_REGIONS is usually: 79 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 80 */ 81 #define MAX_MMAP_REGIONS 6 82 83 /* DTB initialization value */ 84 #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 85 86 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 87 STM32MP_BL2_DTB_SIZE) 88 89 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 90 #define STM32MP_BL33_MAX_SIZE U(0x400000) 91 92 /******************************************************************************* 93 * STM32MP2 RCC 94 ******************************************************************************/ 95 #define RCC_BASE U(0x44200000) 96 97 /******************************************************************************* 98 * STM32MP2 PWR 99 ******************************************************************************/ 100 #define PWR_BASE U(0x44210000) 101 102 /******************************************************************************* 103 * STM32MP2 GPIO 104 ******************************************************************************/ 105 #define GPIOA_BASE U(0x44240000) 106 #define GPIOB_BASE U(0x44250000) 107 #define GPIOC_BASE U(0x44260000) 108 #define GPIOD_BASE U(0x44270000) 109 #define GPIOE_BASE U(0x44280000) 110 #define GPIOF_BASE U(0x44290000) 111 #define GPIOG_BASE U(0x442A0000) 112 #define GPIOH_BASE U(0x442B0000) 113 #define GPIOI_BASE U(0x442C0000) 114 #define GPIOJ_BASE U(0x442D0000) 115 #define GPIOK_BASE U(0x442E0000) 116 #define GPIOZ_BASE U(0x46200000) 117 #define GPIO_BANK_OFFSET U(0x10000) 118 119 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 120 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 121 122 /******************************************************************************* 123 * STM32MP2 UART 124 ******************************************************************************/ 125 #define USART1_BASE U(0x40330000) 126 #define USART2_BASE U(0x400E0000) 127 #define USART3_BASE U(0x400F0000) 128 #define UART4_BASE U(0x40100000) 129 #define UART5_BASE U(0x40110000) 130 #define USART6_BASE U(0x40220000) 131 #define UART7_BASE U(0x40370000) 132 #define UART8_BASE U(0x40380000) 133 #define UART9_BASE U(0x402C0000) 134 #define STM32MP_NB_OF_UART U(9) 135 136 /* For UART crash console */ 137 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 138 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 139 #define STM32MP_DEBUG_USART_BASE USART2_BASE 140 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 141 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 142 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 143 #define DEBUG_UART_TX_GPIO_PORT 4 144 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 145 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 146 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 147 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 148 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 149 #define DEBUG_UART_RST_REG RCC_USART2CFGR 150 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 151 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 152 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 153 154 /******************************************************************************* 155 * STM32MP2 SDMMC 156 ******************************************************************************/ 157 #define STM32MP_SDMMC1_BASE U(0x48220000) 158 #define STM32MP_SDMMC2_BASE U(0x48230000) 159 #define STM32MP_SDMMC3_BASE U(0x48240000) 160 161 /******************************************************************************* 162 * STM32MP2 BSEC / OTP 163 ******************************************************************************/ 164 /* 165 * 367 available OTPs, the other are masked 166 * - ECIES key: 368 to 375 (only readable by bootrom) 167 * - HWKEY: 376 to 383 (never reloadable or readable) 168 */ 169 #define STM32MP2_OTP_MAX_ID U(0x16F) 170 #define STM32MP2_MID_OTP_START U(0x80) 171 #define STM32MP2_UPPER_OTP_START U(0x100) 172 173 /* OTP labels */ 174 #define PART_NUMBER_OTP "part-number-otp" 175 #define PACKAGE_OTP "package-otp" 176 #define HCONF1_OTP "otp124" 177 #define NAND_OTP "otp16" 178 #define NAND2_OTP "otp20" 179 #define BOARD_ID_OTP "board-id" 180 #define UID_OTP "uid-otp" 181 #define LIFECYCLE2_OTP "otp18" 182 #define PKH_OTP "otp144" 183 #define ENCKEY_OTP "otp260" 184 185 /* OTP mask */ 186 /* PACKAGE */ 187 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 188 #define PACKAGE_OTP_PKG_SHIFT U(0) 189 190 /* IWDG OTP */ 191 #define HCONF1_OTP_IWDG_HW_POS U(0) 192 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 193 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 194 195 /* NAND OTP */ 196 /* NAND parameter storage flag */ 197 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 198 199 /* NAND page size in bytes */ 200 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 201 #define NAND_PAGE_SIZE_SHIFT U(29) 202 #define NAND_PAGE_SIZE_2K U(0) 203 #define NAND_PAGE_SIZE_4K U(1) 204 #define NAND_PAGE_SIZE_8K U(2) 205 206 /* NAND block size in pages */ 207 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 208 #define NAND_BLOCK_SIZE_SHIFT U(27) 209 #define NAND_BLOCK_SIZE_64_PAGES U(0) 210 #define NAND_BLOCK_SIZE_128_PAGES U(1) 211 #define NAND_BLOCK_SIZE_256_PAGES U(2) 212 213 /* NAND number of block (in unit of 256 blocks) */ 214 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 215 #define NAND_BLOCK_NB_SHIFT U(19) 216 #define NAND_BLOCK_NB_UNIT U(256) 217 218 /* NAND bus width in bits */ 219 #define NAND_WIDTH_MASK BIT_32(18) 220 #define NAND_WIDTH_SHIFT U(18) 221 222 /* NAND number of ECC bits per 512 bytes */ 223 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 224 #define NAND_ECC_BIT_NB_SHIFT U(15) 225 #define NAND_ECC_BIT_NB_UNSET U(0) 226 #define NAND_ECC_BIT_NB_1_BITS U(1) 227 #define NAND_ECC_BIT_NB_4_BITS U(2) 228 #define NAND_ECC_BIT_NB_8_BITS U(3) 229 #define NAND_ECC_ON_DIE U(4) 230 231 /* NAND number of planes */ 232 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 233 234 /* NAND2 OTP */ 235 #define NAND2_PAGE_SIZE_SHIFT U(16) 236 237 /* NAND2 config distribution */ 238 #define NAND2_CONFIG_DISTRIB BIT_32(0) 239 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 240 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 241 242 /* MONOTONIC OTP */ 243 #define MAX_MONOTONIC_VALUE U(32) 244 245 /* UID OTP */ 246 #define UID_WORD_NB U(3) 247 248 /* Lifecycle OTP */ 249 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 250 251 /******************************************************************************* 252 * STM32MP2 TAMP 253 ******************************************************************************/ 254 #define PLAT_MAX_TAMP_INT U(5) 255 #define PLAT_MAX_TAMP_EXT U(3) 256 #define TAMP_BASE U(0x46010000) 257 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 258 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 259 #define TAMP_BKP_REG_CLK CK_BUS_RTC 260 #define TAMP_BKP_SEC_NUMBER U(10) 261 #define TAMP_COUNTR U(0x40) 262 263 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 264 static inline uintptr_t tamp_bkpr(uint32_t idx) 265 { 266 return TAMP_BKP_REGISTER_BASE + (idx << 2); 267 } 268 #endif 269 270 /******************************************************************************* 271 * STM32MP2 DDRCTRL 272 ******************************************************************************/ 273 #define DDRCTRL_BASE U(0x48040000) 274 275 /******************************************************************************* 276 * STM32MP2 DDRDBG 277 ******************************************************************************/ 278 #define DDRDBG_BASE U(0x48050000) 279 280 /******************************************************************************* 281 * STM32MP2 DDRPHYC 282 ******************************************************************************/ 283 #define DDRPHYC_BASE U(0x48C00000) 284 285 /******************************************************************************* 286 * Miscellaneous STM32MP1 peripherals base address 287 ******************************************************************************/ 288 #define BSEC_BASE U(0x44000000) 289 #define DBGMCU_BASE U(0x4A010000) 290 #define HASH_BASE U(0x42010000) 291 #define RTC_BASE U(0x46000000) 292 #define STGEN_BASE U(0x48080000) 293 #define SYSCFG_BASE U(0x44230000) 294 295 /******************************************************************************* 296 * REGULATORS 297 ******************************************************************************/ 298 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 299 #define PLAT_NB_RDEVS U(19) 300 /* 2 FIXED */ 301 #define PLAT_NB_FIXED_REGUS U(2) 302 /* No GPIO regu */ 303 #define PLAT_NB_GPIO_REGUS U(0) 304 305 /******************************************************************************* 306 * Device Tree defines 307 ******************************************************************************/ 308 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 309 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 310 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 311 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 312 #define DT_UART_COMPAT "st,stm32h7-uart" 313 314 #endif /* STM32MP2_DEF_H */ 315