1# 2# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14# Disable PIE by default. To re-enable it, uncomment next line. 15#ENABLE_PIE := 1 16PROGRAMMABLE_RESET_ADDRESS := 1 17ifeq ($(ENABLE_PIE),1) 18BL2_IN_XIP_MEM := 1 19endif 20 21STM32MP_BL33_EL1 ?= 1 22ifeq ($(STM32MP_BL33_EL1),1) 23INIT_UNUSED_NS_EL2 := 1 24endif 25 26# Disable features unsupported in ARMv8.0 27ENABLE_SPE_FOR_NS := 0 28ENABLE_SVE_FOR_NS := 0 29 30# Default Device tree 31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 32 33STM32MP25 := 1 34 35# STM32 image header version v2.2 36STM32_HEADER_VERSION_MAJOR := 2 37STM32_HEADER_VERSION_MINOR := 2 38 39# Set load address for serial boot devices 40DWL_BUFFER_BASE ?= 0x87000000 41 42# DDR types 43STM32MP_DDR3_TYPE ?= 0 44STM32MP_DDR4_TYPE ?= 0 45STM32MP_LPDDR4_TYPE ?= 0 46ifeq (${STM32MP_DDR3_TYPE},1) 47DDR_TYPE := ddr3 48endif 49ifeq (${STM32MP_DDR4_TYPE},1) 50DDR_TYPE := ddr4 51endif 52ifeq (${STM32MP_LPDDR4_TYPE},1) 53DDR_TYPE := lpddr4 54endif 55 56# DDR features 57STM32MP_DDR_DUAL_AXI_PORT := 1 58STM32MP_DDR_FIP_IO_STORAGE := 1 59 60# Device tree 61BL2_DTSI := stm32mp25-bl2.dtsi 62FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 63BL31_DTSI := stm32mp25-bl31.dtsi 64FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 65 66# Macros and rules to build TF binary 67STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 68STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 69STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 70 71STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 72STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 73STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 74ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 75STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 76STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 77STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 78endif 79FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 80 81# Add the FW_CONFIG to FIP and specify the same to certtool 82$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 83 84# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 85$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG)))) 86 87ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 88# Add the FW_DDR to FIP and specify the same to certtool 89$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 90endif 91 92# Enable flags for C files 93$(eval $(call assert_booleans,\ 94 $(sort \ 95 STM32MP_DDR_DUAL_AXI_PORT \ 96 STM32MP_DDR_FIP_IO_STORAGE \ 97 STM32MP_DDR3_TYPE \ 98 STM32MP_DDR4_TYPE \ 99 STM32MP_LPDDR4_TYPE \ 100 STM32MP25 \ 101 STM32MP_BL33_EL1 \ 102))) 103 104$(eval $(call assert_numerics,\ 105 $(sort \ 106 PLAT_PARTITION_MAX_ENTRIES \ 107 STM32_HEADER_VERSION_MAJOR \ 108 STM32_TF_A_COPIES \ 109))) 110 111$(eval $(call add_defines,\ 112 $(sort \ 113 DWL_BUFFER_BASE \ 114 PLAT_DEF_FIP_UUID \ 115 PLAT_PARTITION_MAX_ENTRIES \ 116 PLAT_TBBR_IMG_DEF \ 117 STM32_TF_A_COPIES \ 118 STM32MP_DDR_DUAL_AXI_PORT \ 119 STM32MP_DDR_FIP_IO_STORAGE \ 120 STM32MP_DDR3_TYPE \ 121 STM32MP_DDR4_TYPE \ 122 STM32MP_LPDDR4_TYPE \ 123 STM32MP25 \ 124 STM32MP_BL33_EL1 \ 125))) 126 127# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 128# Disable mbranch-protection to avoid adding useless code 129TF_CFLAGS += -mbranch-protection=none 130 131# Include paths and source files 132PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 133PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 134PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 135 136PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 137PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 138PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 139 140PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 141 drivers/st/pmic/stpmic2.c \ 142 143PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 144 145PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 146 147PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 148 drivers/st/reset/stm32mp2_reset.c \ 149 plat/st/stm32mp2/stm32mp2_syscfg.c 150 151PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 152 drivers/st/clk/clk-stm32mp2.c 153 154BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 155 156BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 157 plat/st/stm32mp2/plat_ddr.c 158 159ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 160BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 161endif 162 163ifeq (${STM32MP_USB_PROGRAMMER},1) 164BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 165endif 166 167BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 168 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 169 drivers/st/ddr/stm32mp2_ram.c 170 171BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 172 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 173 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 174 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 175 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 176 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 177 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 178 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 179 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 180 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 181 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 182 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 183 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 184 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 185 186BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 187 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 188 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 189 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 190 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 191 192# BL31 sources 193BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 194 195BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 196 plat/st/stm32mp2/stm32mp2_pm.c \ 197 plat/st/stm32mp2/stm32mp2_topology.c 198# Generic GIC v2 199include drivers/arm/gic/v2/gicv2.mk 200 201BL31_SOURCES += ${GICV2_SOURCES} \ 202 plat/common/plat_gicv2.c \ 203 plat/st/common/stm32mp_gic.c 204 205# Generic PSCI 206BL31_SOURCES += plat/common/plat_psci_common.c 207 208BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \ 209 plat/st/stm32mp2/services/stgen_svc.c \ 210 plat/st/stm32mp2/services/stm32mp2_svc_setup.c 211 212# Arm Archtecture services 213BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c 214 215# Compilation rules 216.PHONY: check_ddr_type 217bl2: check_ddr_type 218 219check_ddr_type: 220 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 221 $(STM32MP_DDR4_TYPE) + \ 222 $(STM32MP_LPDDR4_TYPE))))) 223 @if [ ${DDR_TYPE} != 1 ]; then \ 224 echo "One and only one DDR type must be defined"; \ 225 false; \ 226 fi 227 228# Create DTB file for BL31 229${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 230 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 231 @echo '#include "${BL31_DTSI}"' >> $@ 232 233include plat/st/common/common_rules.mk 234