xref: /rk3399_ARM-atf/plat/st/stm32mp2/platform.mk (revision e577ca36668c33a6a28dbbf152c9892b4fe79611)
135527fb4SYann Gautier#
2ac9abe7eSMaxime Méré# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
335527fb4SYann Gautier#
435527fb4SYann Gautier# SPDX-License-Identifier: BSD-3-Clause
535527fb4SYann Gautier#
635527fb4SYann Gautier
766b4c5c5SYann Gautier# Extra partitions used to find FIP, contains:
866b4c5c5SYann Gautier# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
966b4c5c5SYann GautierSTM32_EXTRA_PARTS		:=	6
1066b4c5c5SYann Gautier
1135527fb4SYann Gautierinclude plat/st/common/common.mk
1235527fb4SYann Gautier
1335527fb4SYann GautierCRASH_REPORTING			:=	1
14ac9abe7eSMaxime Méré# Disable PIE by default. To re-enable it, uncomment next line.
15ac9abe7eSMaxime Méré#ENABLE_PIE			:=	1
1635527fb4SYann GautierPROGRAMMABLE_RESET_ADDRESS	:=	1
17ac9abe7eSMaxime Méréifeq ($(ENABLE_PIE),1)
18db77f8bfSYann GautierBL2_IN_XIP_MEM			:=	1
19ac9abe7eSMaxime Méréendif
2035527fb4SYann Gautier
21c900760dSYann GautierSTM32MP_BL33_EL1		?=	1
22c900760dSYann Gautierifeq ($(STM32MP_BL33_EL1),1)
23c900760dSYann GautierINIT_UNUSED_NS_EL2		:=	1
24c900760dSYann Gautierendif
25c900760dSYann Gautier
26128df965SYann Gautier# Disable features unsupported in ARMv8.0
27128df965SYann GautierENABLE_SPE_FOR_NS		:=	0
28128df965SYann GautierENABLE_SVE_FOR_NS		:=	0
29128df965SYann Gautier
3035527fb4SYann Gautier# Default Device tree
3135527fb4SYann GautierDTB_FILE_NAME			?=	stm32mp257f-ev1.dtb
3235527fb4SYann Gautier
3307759f2bSYann GautierSTM32MP21			?=	0
34*e577ca36SNicolas Le BayonSTM32MP23			?=	0
3507759f2bSYann GautierSTM32MP25			?=	0
3635527fb4SYann Gautier
3707759f2bSYann Gautierifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
3807759f2bSYann GautierSTM32MP21			:=	1
3907759f2bSYann Gautierendif
40*e577ca36SNicolas Le Bayonifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
41*e577ca36SNicolas Le BayonSTM32MP23			:=	1
42*e577ca36SNicolas Le Bayonendif
4307759f2bSYann Gautierifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
4407759f2bSYann GautierSTM32MP25			:=	1
4507759f2bSYann Gautierendif
46*e577ca36SNicolas Le Bayonifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
4707759f2bSYann Gautier$(warning STM32MP21=$(STM32MP21))
48*e577ca36SNicolas Le Bayon$(warning STM32MP23=$(STM32MP23))
4907759f2bSYann Gautier$(warning STM32MP25=$(STM32MP25))
5007759f2bSYann Gautier$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
51*e577ca36SNicolas Le Bayon$(error Cannot enable more than one STM32MP2x flag)
5207759f2bSYann Gautierendif
5307759f2bSYann Gautier
5407759f2bSYann Gautier# STM32 image header version v2.2 or v2.3 for STM32MP21
5535527fb4SYann GautierSTM32_HEADER_VERSION_MAJOR	:=	2
5607759f2bSYann Gautierifeq ($(STM32MP21),1)
5707759f2bSYann GautierSTM32_HEADER_VERSION_MINOR	:=	3
5807759f2bSYann Gautierelse
5935527fb4SYann GautierSTM32_HEADER_VERSION_MINOR	:=	2
6007759f2bSYann Gautierendif
6135527fb4SYann Gautier
622e905c06SYann Gautier# Set load address for serial boot devices
632e905c06SYann GautierDWL_BUFFER_BASE 		?=	0x87000000
642e905c06SYann Gautier
65d07e9467SNicolas Le Bayon# DDR types
66d07e9467SNicolas Le BayonSTM32MP_DDR3_TYPE		?=	0
67d07e9467SNicolas Le BayonSTM32MP_DDR4_TYPE		?=	0
68d07e9467SNicolas Le BayonSTM32MP_LPDDR4_TYPE		?=	0
69d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR3_TYPE},1)
70d07e9467SNicolas Le BayonDDR_TYPE			:=	ddr3
71d07e9467SNicolas Le Bayonendif
72d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR4_TYPE},1)
73d07e9467SNicolas Le BayonDDR_TYPE			:=	ddr4
74d07e9467SNicolas Le Bayonendif
75d07e9467SNicolas Le Bayonifeq (${STM32MP_LPDDR4_TYPE},1)
76d07e9467SNicolas Le BayonDDR_TYPE			:=	lpddr4
77d07e9467SNicolas Le Bayonendif
78d07e9467SNicolas Le Bayon
79ae84525fSMaxime Méré# DDR features
8079629b1aSNicolas Le BayonSTM32MP_DDR_DUAL_AXI_PORT	:=	1
81ae84525fSMaxime MéréSTM32MP_DDR_FIP_IO_STORAGE	:=	1
82ae84525fSMaxime Méré
83e5839ed7SYann Gautier# Device tree
84e5839ed7SYann GautierBL2_DTSI			:=	stm32mp25-bl2.dtsi
85e5839ed7SYann GautierFDT_SOURCES			:=	$(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
8627dd11dbSMaxime MéréBL31_DTSI			:=	stm32mp25-bl31.dtsi
8727dd11dbSMaxime MéréFDT_SOURCES			+=	$(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
88e5839ed7SYann Gautier
89e5839ed7SYann Gautier# Macros and rules to build TF binary
90e5839ed7SYann GautierSTM32_TF_STM32			:=	$(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
91e5839ed7SYann GautierSTM32_LD_FILE			:=	plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
92e5839ed7SYann GautierSTM32_BINARY_MAPPING		:=	plat/st/stm32mp2/${ARCH}/stm32mp2.S
93e5839ed7SYann Gautier
945af9369cSYann GautierSTM32MP_FW_CONFIG_NAME		:=	$(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
955af9369cSYann GautierSTM32MP_FW_CONFIG		:=	${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
9627dd11dbSMaxime MéréSTM32MP_SOC_FW_CONFIG		:=	$(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
97ae84525fSMaxime Méréifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
98ae84525fSMaxime MéréSTM32MP_DDR_FW_PATH		?=	drivers/st/ddr/phy/firmware/bin/stm32mp2
99ae84525fSMaxime MéréSTM32MP_DDR_FW_NAME		:=	${DDR_TYPE}_pmu_train.bin
100ae84525fSMaxime MéréSTM32MP_DDR_FW			:=	${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
101ae84525fSMaxime Méréendif
1025af9369cSYann GautierFDT_SOURCES			+=	$(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
103f15f1c62SYann Gautier
1045af9369cSYann Gautier# Add the FW_CONFIG to FIP and specify the same to certtool
1055af9369cSYann Gautier$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
106f15f1c62SYann Gautier
10727dd11dbSMaxime Méré# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
108f15f1c62SYann Gautier$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG))))
109f15f1c62SYann Gautier
110ae84525fSMaxime Méréifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
111ae84525fSMaxime Méré# Add the FW_DDR to FIP and specify the same to certtool
112ae84525fSMaxime Méré$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
113ae84525fSMaxime Méréendif
1145af9369cSYann Gautier
115d59dd96dSBoerge Struempfel# Ultratronik Specific Boards
116d59dd96dSBoerge Struempfelifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly)
117d59dd96dSBoerge StruempfelULTRA_FLY := 1
118d59dd96dSBoerge Struempfel$(eval $(call assert_booleans,\
119d59dd96dSBoerge Struempfel	$(sort \
120d59dd96dSBoerge Struempfel		ULTRA_FLY \
121d59dd96dSBoerge Struempfel	)))
122d59dd96dSBoerge Struempfel$(eval $(call add_defines,\
123d59dd96dSBoerge Struempfel	$(sort \
124d59dd96dSBoerge Struempfel		ULTRA_FLY \
125d59dd96dSBoerge Struempfel	)))
126d59dd96dSBoerge Struempfelendif
127d59dd96dSBoerge Struempfel
128db77f8bfSYann Gautier# Enable flags for C files
129db77f8bfSYann Gautier$(eval $(call assert_booleans,\
130db77f8bfSYann Gautier	$(sort \
13179629b1aSNicolas Le Bayon		STM32MP_DDR_DUAL_AXI_PORT \
132ae84525fSMaxime Méré		STM32MP_DDR_FIP_IO_STORAGE \
133d07e9467SNicolas Le Bayon		STM32MP_DDR3_TYPE \
134d07e9467SNicolas Le Bayon		STM32MP_DDR4_TYPE \
135d07e9467SNicolas Le Bayon		STM32MP_LPDDR4_TYPE \
13607759f2bSYann Gautier		STM32MP21 \
137*e577ca36SNicolas Le Bayon		STM32MP23 \
138db77f8bfSYann Gautier		STM32MP25 \
139c900760dSYann Gautier		STM32MP_BL33_EL1 \
140db77f8bfSYann Gautier)))
141db77f8bfSYann Gautier
142db77f8bfSYann Gautier$(eval $(call assert_numerics,\
143db77f8bfSYann Gautier	$(sort \
144db77f8bfSYann Gautier		PLAT_PARTITION_MAX_ENTRIES \
145db77f8bfSYann Gautier		STM32_HEADER_VERSION_MAJOR \
146db77f8bfSYann Gautier		STM32_TF_A_COPIES \
147db77f8bfSYann Gautier)))
148db77f8bfSYann Gautier
1492e905c06SYann Gautier$(eval $(call add_defines,\
1502e905c06SYann Gautier	$(sort \
1512e905c06SYann Gautier		DWL_BUFFER_BASE \
152ae84525fSMaxime Méré		PLAT_DEF_FIP_UUID \
153db77f8bfSYann Gautier		PLAT_PARTITION_MAX_ENTRIES \
154db77f8bfSYann Gautier		PLAT_TBBR_IMG_DEF \
155db77f8bfSYann Gautier		STM32_TF_A_COPIES \
15679629b1aSNicolas Le Bayon		STM32MP_DDR_DUAL_AXI_PORT \
157ae84525fSMaxime Méré		STM32MP_DDR_FIP_IO_STORAGE \
158d07e9467SNicolas Le Bayon		STM32MP_DDR3_TYPE \
159d07e9467SNicolas Le Bayon		STM32MP_DDR4_TYPE \
160d07e9467SNicolas Le Bayon		STM32MP_LPDDR4_TYPE \
16107759f2bSYann Gautier		STM32MP21 \
162*e577ca36SNicolas Le Bayon		STM32MP23 \
163db77f8bfSYann Gautier		STM32MP25 \
164c900760dSYann Gautier		STM32MP_BL33_EL1 \
1652e905c06SYann Gautier)))
1662e905c06SYann Gautier
16735527fb4SYann Gautier# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
16835527fb4SYann Gautier# Disable mbranch-protection to avoid adding useless code
16935527fb4SYann GautierTF_CFLAGS			+=	-mbranch-protection=none
17035527fb4SYann Gautier
17135527fb4SYann Gautier# Include paths and source files
17235527fb4SYann GautierPLAT_INCLUDES			+=	-Iplat/st/stm32mp2/include/
17379629b1aSNicolas Le BayonPLAT_INCLUDES			+=	-Idrivers/st/ddr/phy/phyinit/include/
17479629b1aSNicolas Le BayonPLAT_INCLUDES			+=	-Idrivers/st/ddr/phy/firmware/include/
17535527fb4SYann Gautier
17635527fb4SYann GautierPLAT_BL_COMMON_SOURCES		+=	lib/cpus/${ARCH}/cortex_a35.S
17787a940e0SYann GautierPLAT_BL_COMMON_SOURCES		+=	drivers/st/uart/${ARCH}/stm32_console.S
17835527fb4SYann GautierPLAT_BL_COMMON_SOURCES		+=	plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
17935527fb4SYann Gautier
180817f42f0SPascal PailletPLAT_BL_COMMON_SOURCES		+=	drivers/st/pmic/stm32mp_pmic2.c				\
181817f42f0SPascal Paillet					drivers/st/pmic/stpmic2.c				\
182817f42f0SPascal Paillet
183817f42f0SPascal PailletPLAT_BL_COMMON_SOURCES		+=	drivers/st/i2c/stm32_i2c.c
184817f42f0SPascal Paillet
185db77f8bfSYann GautierPLAT_BL_COMMON_SOURCES		+=	plat/st/stm32mp2/stm32mp2_private.c
186db77f8bfSYann Gautier
187f829d7dfSGabriel FernandezPLAT_BL_COMMON_SOURCES		+=	drivers/st/bsec/bsec3.c					\
188154e6e62SYann Gautier					drivers/st/reset/stm32mp2_reset.c			\
189154e6e62SYann Gautier					plat/st/stm32mp2/stm32mp2_syscfg.c
190197ac780SYann Gautier
191615f31feSGabriel FernandezPLAT_BL_COMMON_SOURCES		+=	drivers/st/clk/clk-stm32-core.c				\
192615f31feSGabriel Fernandez					drivers/st/clk/clk-stm32mp2.c
193615f31feSGabriel Fernandez
19435527fb4SYann GautierBL2_SOURCES			+=	plat/st/stm32mp2/plat_bl2_mem_params_desc.c
195db77f8bfSYann Gautier
196e2d6e5e2SPascal PailletBL2_SOURCES			+=	plat/st/stm32mp2/bl2_plat_setup.c			\
197e2d6e5e2SPascal Paillet					plat/st/stm32mp2/plat_ddr.c
19835527fb4SYann Gautier
199db77f8bfSYann Gautierifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
200db77f8bfSYann GautierBL2_SOURCES			+=	drivers/st/mmc/stm32_sdmmc2.c
201db77f8bfSYann Gautierendif
202db77f8bfSYann Gautier
2032e905c06SYann Gautierifeq (${STM32MP_USB_PROGRAMMER},1)
2042e905c06SYann GautierBL2_SOURCES			+=	plat/st/stm32mp2/stm32mp2_usb_dfu.c
2052e905c06SYann Gautierendif
2062e905c06SYann Gautier
20779629b1aSNicolas Le BayonBL2_SOURCES			+=	drivers/st/ddr/stm32mp2_ddr.c				\
20879629b1aSNicolas Le Bayon					drivers/st/ddr/stm32mp2_ddr_helpers.c			\
20979629b1aSNicolas Le Bayon					drivers/st/ddr/stm32mp2_ram.c
21079629b1aSNicolas Le Bayon
21179629b1aSNicolas Le BayonBL2_SOURCES			+=	drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c				\
21279629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c					\
21379629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c				\
21479629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c				\
21579629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c				\
21679629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c				\
21779629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c				\
21879629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c			\
21979629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c				\
22079629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c			\
22179629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c				\
22279629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c				\
22379629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c	\
22479629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
22579629b1aSNicolas Le Bayon
22679629b1aSNicolas Le BayonBL2_SOURCES			+=	drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c				\
22779629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c				\
22879629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c				\
22979629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c				\
23079629b1aSNicolas Le Bayon					drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
2315e0be8c0SYann Gautier
23203020b66SYann Gautier# BL31 sources
23303020b66SYann GautierBL31_SOURCES			+=	${FDT_WRAPPERS_SOURCES}
23403020b66SYann Gautier
23503020b66SYann GautierBL31_SOURCES			+=	plat/st/stm32mp2/bl31_plat_setup.c			\
23603020b66SYann Gautier					plat/st/stm32mp2/stm32mp2_pm.c				\
23703020b66SYann Gautier					plat/st/stm32mp2/stm32mp2_topology.c
23803020b66SYann Gautier# Generic GIC v2
23903020b66SYann Gautierinclude drivers/arm/gic/v2/gicv2.mk
24003020b66SYann Gautier
24103020b66SYann GautierBL31_SOURCES			+=	${GICV2_SOURCES}					\
24203020b66SYann Gautier					plat/common/plat_gicv2.c				\
24303020b66SYann Gautier					plat/st/common/stm32mp_gic.c
24403020b66SYann Gautier
24503020b66SYann Gautier# Generic PSCI
24603020b66SYann GautierBL31_SOURCES			+=	plat/common/plat_psci_common.c
24703020b66SYann Gautier
248f55b136aSGatien ChevallierBL31_SOURCES			+=	plat/st/common/stm32mp_svc_setup.c			\
2497f41506fSGatien Chevallier					plat/st/stm32mp2/services/stgen_svc.c			\
250f55b136aSGatien Chevallier					plat/st/stm32mp2/services/stm32mp2_svc_setup.c
251f55b136aSGatien Chevallier
252f55b136aSGatien Chevallier# Arm Archtecture services
253f55b136aSGatien ChevallierBL31_SOURCES			+=	services/arm_arch_svc/arm_arch_svc_setup.c
254f55b136aSGatien Chevallier
255db77f8bfSYann Gautier# Compilation rules
256d07e9467SNicolas Le Bayon.PHONY: check_ddr_type
257d07e9467SNicolas Le Bayonbl2: check_ddr_type
258d07e9467SNicolas Le Bayon
259d07e9467SNicolas Le Bayoncheck_ddr_type:
260d07e9467SNicolas Le Bayon	$(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
261d07e9467SNicolas Le Bayon					   $(STM32MP_DDR4_TYPE) + \
262d07e9467SNicolas Le Bayon					   $(STM32MP_LPDDR4_TYPE)))))
263d07e9467SNicolas Le Bayon	@if [ ${DDR_TYPE} != 1 ]; then \
264d07e9467SNicolas Le Bayon		echo "One and only one DDR type must be defined"; \
265d07e9467SNicolas Le Bayon		false; \
266d07e9467SNicolas Le Bayon	fi
267d07e9467SNicolas Le Bayon
26827dd11dbSMaxime Méré# Create DTB file for BL31
26927dd11dbSMaxime Méré${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
27027dd11dbSMaxime Méré	@echo '#include "$(patsubst fdts/%,%,$<)"' > $@
27127dd11dbSMaxime Méré	@echo '#include "${BL31_DTSI}"' >> $@
27227dd11dbSMaxime Méré
27335527fb4SYann Gautierinclude plat/st/common/common_rules.mk
274