xref: /rk3399_ARM-atf/plat/st/stm32mp2/include/plat_tbbr_img_def.h (revision ccd580c453d5bf6daa114feca108e295e02a62eb)
1db77f8bfSYann Gautier /*
2db77f8bfSYann Gautier  * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
3db77f8bfSYann Gautier  *
4db77f8bfSYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5db77f8bfSYann Gautier  */
6db77f8bfSYann Gautier 
7db77f8bfSYann Gautier #ifndef PLAT_TBBR_IMG_DEF_H
8db77f8bfSYann Gautier #define PLAT_TBBR_IMG_DEF_H
9db77f8bfSYann Gautier 
10db77f8bfSYann Gautier #include <export/common/tbbr/tbbr_img_def_exp.h>
11db77f8bfSYann Gautier 
12db77f8bfSYann Gautier /* Undef the existing values */
13db77f8bfSYann Gautier #undef BKUP_FWU_METADATA_IMAGE_ID
14db77f8bfSYann Gautier #undef FWU_METADATA_IMAGE_ID
15db77f8bfSYann Gautier #undef FW_CONFIG_ID
16db77f8bfSYann Gautier #undef ENC_IMAGE_ID
17db77f8bfSYann Gautier #undef GPT_IMAGE_ID
18db77f8bfSYann Gautier #undef NT_FW_CONFIG_ID
19db77f8bfSYann Gautier #undef SOC_FW_CONFIG_ID
20db77f8bfSYann Gautier #undef TB_FW_CONFIG_ID
21db77f8bfSYann Gautier #undef HW_CONFIG_ID
22db77f8bfSYann Gautier #undef TRUSTED_BOOT_FW_CERT_ID
23db77f8bfSYann Gautier #undef SOC_FW_CONTENT_CERT_ID
24db77f8bfSYann Gautier #undef BL32_EXTRA1_IMAGE_ID
25db77f8bfSYann Gautier #undef TOS_FW_CONFIG_ID
26db77f8bfSYann Gautier 
27db77f8bfSYann Gautier /* Define the STM32MP2 used ID */
28db77f8bfSYann Gautier #define FW_CONFIG_ID			U(1)
29db77f8bfSYann Gautier #define HW_CONFIG_ID			U(2)
30db77f8bfSYann Gautier #define ENC_IMAGE_ID			U(6)
31db77f8bfSYann Gautier #define BL32_EXTRA1_IMAGE_ID		U(8)
32db77f8bfSYann Gautier #define FWU_METADATA_IMAGE_ID		U(12)
33db77f8bfSYann Gautier #define BKUP_FWU_METADATA_IMAGE_ID	U(13)
34db77f8bfSYann Gautier #define TOS_FW_CONFIG_ID		U(16)
35db77f8bfSYann Gautier #define NT_FW_CONFIG_ID			U(18)
36db77f8bfSYann Gautier #define SOC_FW_CONFIG_ID		U(19)
37db77f8bfSYann Gautier #define TB_FW_CONFIG_ID			U(20)
38db77f8bfSYann Gautier #define TRUSTED_BOOT_FW_CERT_ID		U(21)
39db77f8bfSYann Gautier #define SOC_FW_CONTENT_CERT_ID		U(23)
40db77f8bfSYann Gautier #define STM32MP_CONFIG_CERT_ID		U(24)
41db77f8bfSYann Gautier #define GPT_IMAGE_ID			U(25)
42db77f8bfSYann Gautier 
43*ae84525fSMaxime Méré #if STM32MP_DDR_FIP_IO_STORAGE
44*ae84525fSMaxime Méré #define DDR_FW_ID			U(26)
45*ae84525fSMaxime Méré /* Increase the MAX_NUMBER_IDS to match the authentication pool required */
46*ae84525fSMaxime Méré #define MAX_NUMBER_IDS			U(27)
47*ae84525fSMaxime Méré 
48*ae84525fSMaxime Méré #else
49db77f8bfSYann Gautier /* Increase the MAX_NUMBER_IDS to match the authentication pool required */
50db77f8bfSYann Gautier #define MAX_NUMBER_IDS			U(26)
51db77f8bfSYann Gautier 
52*ae84525fSMaxime Méré #endif
53*ae84525fSMaxime Méré 
54db77f8bfSYann Gautier #endif /* PLAT_TBBR_IMG_DEF_H */
55db77f8bfSYann Gautier 
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