1*03020b66SYann Gautier /* 2*03020b66SYann Gautier * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3*03020b66SYann Gautier * 4*03020b66SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*03020b66SYann Gautier */ 6*03020b66SYann Gautier 7*03020b66SYann Gautier #include <assert.h> 8*03020b66SYann Gautier #include <stdint.h> 9*03020b66SYann Gautier 10*03020b66SYann Gautier #include <common/bl_common.h> 11*03020b66SYann Gautier #include <drivers/st/stm32_console.h> 12*03020b66SYann Gautier #include <lib/xlat_tables/xlat_tables_v2.h> 13*03020b66SYann Gautier #include <plat/common/platform.h> 14*03020b66SYann Gautier 15*03020b66SYann Gautier #include <platform_def.h> 16*03020b66SYann Gautier 17*03020b66SYann Gautier void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 18*03020b66SYann Gautier u_register_t arg2, u_register_t arg3) 19*03020b66SYann Gautier { 20*03020b66SYann Gautier bl_params_t *params_from_bl2; 21*03020b66SYann Gautier int ret; 22*03020b66SYann Gautier 23*03020b66SYann Gautier /* 24*03020b66SYann Gautier * Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will 25*03020b66SYann Gautier * be later used as non-secure. 26*03020b66SYann Gautier */ 27*03020b66SYann Gautier inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 28*03020b66SYann Gautier STM32MP_SYSRAM_SIZE / 2U); 29*03020b66SYann Gautier 30*03020b66SYann Gautier mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 31*03020b66SYann Gautier BL_CODE_END - BL_CODE_BASE, 32*03020b66SYann Gautier MT_CODE | MT_SECURE); 33*03020b66SYann Gautier 34*03020b66SYann Gautier #if USE_COHERENT_MEM 35*03020b66SYann Gautier /* Map coherent memory */ 36*03020b66SYann Gautier mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 37*03020b66SYann Gautier BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 38*03020b66SYann Gautier MT_DEVICE | MT_RW | MT_SECURE); 39*03020b66SYann Gautier #endif 40*03020b66SYann Gautier 41*03020b66SYann Gautier configure_mmu(); 42*03020b66SYann Gautier 43*03020b66SYann Gautier /* 44*03020b66SYann Gautier * Map upper SYSRAM where bl_params_t are stored in BL2 45*03020b66SYann Gautier */ 46*03020b66SYann Gautier ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 47*03020b66SYann Gautier STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 48*03020b66SYann Gautier STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE); 49*03020b66SYann Gautier if (ret < 0) { 50*03020b66SYann Gautier ERROR("BL2 params area mapping: %d\n", ret); 51*03020b66SYann Gautier panic(); 52*03020b66SYann Gautier } 53*03020b66SYann Gautier 54*03020b66SYann Gautier assert(arg0 != 0UL); 55*03020b66SYann Gautier params_from_bl2 = (bl_params_t *)arg0; 56*03020b66SYann Gautier assert(params_from_bl2 != NULL); 57*03020b66SYann Gautier assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 58*03020b66SYann Gautier assert(params_from_bl2->h.version >= VERSION_2); 59*03020b66SYann Gautier 60*03020b66SYann Gautier bl_params_node_t *bl_params = params_from_bl2->head; 61*03020b66SYann Gautier 62*03020b66SYann Gautier while (bl_params != NULL) { 63*03020b66SYann Gautier bl_params = bl_params->next_params_info; 64*03020b66SYann Gautier } 65*03020b66SYann Gautier 66*03020b66SYann Gautier ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 67*03020b66SYann Gautier STM32MP_SYSRAM_SIZE / 2U); 68*03020b66SYann Gautier if (ret < 0) { 69*03020b66SYann Gautier ERROR("BL2 params area unmapping: %d\n", ret); 70*03020b66SYann Gautier panic(); 71*03020b66SYann Gautier } 72*03020b66SYann Gautier } 73*03020b66SYann Gautier 74*03020b66SYann Gautier void bl31_plat_arch_setup(void) 75*03020b66SYann Gautier { 76*03020b66SYann Gautier } 77*03020b66SYann Gautier 78*03020b66SYann Gautier void bl31_platform_setup(void) 79*03020b66SYann Gautier { 80*03020b66SYann Gautier } 81*03020b66SYann Gautier 82*03020b66SYann Gautier entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 83*03020b66SYann Gautier { 84*03020b66SYann Gautier return NULL; 85*03020b66SYann Gautier } 86