1*35527fb4SYann Gautier/* 2*35527fb4SYann Gautier * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3*35527fb4SYann Gautier * 4*35527fb4SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*35527fb4SYann Gautier */ 6*35527fb4SYann Gautier 7*35527fb4SYann Gautier#include <asm_macros.S> 8*35527fb4SYann Gautier 9*35527fb4SYann Gautier#include <platform_def.h> 10*35527fb4SYann Gautier 11*35527fb4SYann Gautier .globl platform_mem_init 12*35527fb4SYann Gautier .globl plat_secondary_cold_boot_setup 13*35527fb4SYann Gautier .globl plat_is_my_cpu_primary 14*35527fb4SYann Gautier .globl plat_crash_console_init 15*35527fb4SYann Gautier .globl plat_crash_console_flush 16*35527fb4SYann Gautier .globl plat_crash_console_putc 17*35527fb4SYann Gautier 18*35527fb4SYann Gautierfunc platform_mem_init 19*35527fb4SYann Gautier /* Nothing to do, don't need to init SYSRAM */ 20*35527fb4SYann Gautier ret 21*35527fb4SYann Gautierendfunc platform_mem_init 22*35527fb4SYann Gautier 23*35527fb4SYann Gautier /* --------------------------------------------- 24*35527fb4SYann Gautier * void plat_secondary_cold_boot_setup (void); 25*35527fb4SYann Gautier * 26*35527fb4SYann Gautier * Set secondary core in WFI waiting for core reset. 27*35527fb4SYann Gautier * --------------------------------------------- 28*35527fb4SYann Gautier */ 29*35527fb4SYann Gautierfunc plat_secondary_cold_boot_setup 30*35527fb4SYann Gautier dsb sy 31*35527fb4SYann Gautier wfi 32*35527fb4SYann Gautier /* This shouldn't be reached */ 33*35527fb4SYann Gautier b . 34*35527fb4SYann Gautierendfunc plat_secondary_cold_boot_setup 35*35527fb4SYann Gautier 36*35527fb4SYann Gautier /* ---------------------------------------------- 37*35527fb4SYann Gautier * unsigned int plat_is_my_cpu_primary(void); 38*35527fb4SYann Gautier * This function checks if this is the primary CPU 39*35527fb4SYann Gautier * ---------------------------------------------- 40*35527fb4SYann Gautier */ 41*35527fb4SYann Gautierfunc plat_is_my_cpu_primary 42*35527fb4SYann Gautier mrs x0, mpidr_el1 43*35527fb4SYann Gautier and x0, x0, #(MPIDR_CPU_MASK) 44*35527fb4SYann Gautier cmp x0, #STM32MP_PRIMARY_CPU 45*35527fb4SYann Gautier cset x0, eq 46*35527fb4SYann Gautier ret 47*35527fb4SYann Gautierendfunc plat_is_my_cpu_primary 48*35527fb4SYann Gautier 49*35527fb4SYann Gautier /* --------------------------------------------- 50*35527fb4SYann Gautier * int plat_crash_console_init(void) 51*35527fb4SYann Gautier * 52*35527fb4SYann Gautier * Initialize the crash console without a C Runtime stack. 53*35527fb4SYann Gautier * --------------------------------------------- 54*35527fb4SYann Gautier */ 55*35527fb4SYann Gautierfunc plat_crash_console_init 56*35527fb4SYann Gautierendfunc plat_crash_console_init 57*35527fb4SYann Gautier 58*35527fb4SYann Gautierfunc plat_crash_console_flush 59*35527fb4SYann Gautierendfunc plat_crash_console_flush 60*35527fb4SYann Gautier 61*35527fb4SYann Gautierfunc plat_crash_console_putc 62*35527fb4SYann Gautierendfunc plat_crash_console_putc 63*35527fb4SYann Gautier 64