1*e5839ed7SYann Gautier/* 2*e5839ed7SYann Gautier * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3*e5839ed7SYann Gautier * 4*e5839ed7SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*e5839ed7SYann Gautier */ 6*e5839ed7SYann Gautier 7*e5839ed7SYann Gautier#ifndef STM32MP2_LD_S 8*e5839ed7SYann Gautier#define STM32MP2_LD_S 9*e5839ed7SYann Gautier 10*e5839ed7SYann Gautier#include <lib/xlat_tables/xlat_tables_defs.h> 11*e5839ed7SYann Gautier#include <platform_def.h> 12*e5839ed7SYann Gautier 13*e5839ed7SYann GautierOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 14*e5839ed7SYann GautierOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 15*e5839ed7SYann Gautier 16*e5839ed7SYann GautierENTRY(__BL2_IMAGE_START__) 17*e5839ed7SYann Gautier 18*e5839ed7SYann GautierMEMORY { 19*e5839ed7SYann Gautier HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE 20*e5839ed7SYann Gautier RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE 21*e5839ed7SYann Gautier} 22*e5839ed7SYann Gautier 23*e5839ed7SYann GautierSECTIONS 24*e5839ed7SYann Gautier{ 25*e5839ed7SYann Gautier /* 26*e5839ed7SYann Gautier * TF mapping must conform to ROM code specification. 27*e5839ed7SYann Gautier */ 28*e5839ed7SYann Gautier .header : { 29*e5839ed7SYann Gautier __HEADER_START__ = .; 30*e5839ed7SYann Gautier KEEP(*(.header)) 31*e5839ed7SYann Gautier . = ALIGN(4); 32*e5839ed7SYann Gautier __HEADER_END__ = .; 33*e5839ed7SYann Gautier } >HEADER 34*e5839ed7SYann Gautier 35*e5839ed7SYann Gautier . = STM32MP_BINARY_BASE; 36*e5839ed7SYann Gautier .data . : { 37*e5839ed7SYann Gautier . = ALIGN(PAGE_SIZE); 38*e5839ed7SYann Gautier __DATA_START__ = .; 39*e5839ed7SYann Gautier *(.data*) 40*e5839ed7SYann Gautier 41*e5839ed7SYann Gautier /* 42*e5839ed7SYann Gautier * dtb. 43*e5839ed7SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 44*e5839ed7SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 45*e5839ed7SYann Gautier */ 46*e5839ed7SYann Gautier . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); 47*e5839ed7SYann Gautier __DTB_IMAGE_START__ = .; 48*e5839ed7SYann Gautier *(.dtb_image*) 49*e5839ed7SYann Gautier __DTB_IMAGE_END__ = .; 50*e5839ed7SYann Gautier 51*e5839ed7SYann Gautier /* 52*e5839ed7SYann Gautier * bl2. 53*e5839ed7SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 54*e5839ed7SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 55*e5839ed7SYann Gautier */ 56*e5839ed7SYann Gautier#if SEPARATE_CODE_AND_RODATA 57*e5839ed7SYann Gautier . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE ); 58*e5839ed7SYann Gautier#else 59*e5839ed7SYann Gautier . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE ); 60*e5839ed7SYann Gautier#endif 61*e5839ed7SYann Gautier __BL2_IMAGE_START__ = .; 62*e5839ed7SYann Gautier *(.bl2_image*) 63*e5839ed7SYann Gautier __BL2_IMAGE_END__ = .; 64*e5839ed7SYann Gautier 65*e5839ed7SYann Gautier __DATA_END__ = .; 66*e5839ed7SYann Gautier } >RAM 67*e5839ed7SYann Gautier 68*e5839ed7SYann Gautier __TF_END__ = .; 69*e5839ed7SYann Gautier 70*e5839ed7SYann Gautier} 71*e5839ed7SYann Gautier#endif /* STM32MP2_LD_S */ 72