1e5839ed7SYann Gautier/* 267788359SYann Gautier * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3e5839ed7SYann Gautier * 4e5839ed7SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5e5839ed7SYann Gautier */ 6e5839ed7SYann Gautier 7e5839ed7SYann Gautier#ifndef STM32MP2_LD_S 8e5839ed7SYann Gautier#define STM32MP2_LD_S 9e5839ed7SYann Gautier 10e5839ed7SYann Gautier#include <lib/xlat_tables/xlat_tables_defs.h> 11e5839ed7SYann Gautier#include <platform_def.h> 12e5839ed7SYann Gautier 13e5839ed7SYann GautierOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 14e5839ed7SYann GautierOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 15e5839ed7SYann Gautier 16e5839ed7SYann GautierENTRY(__BL2_IMAGE_START__) 17e5839ed7SYann Gautier 18e5839ed7SYann GautierMEMORY { 19e5839ed7SYann Gautier HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE 20e5839ed7SYann Gautier RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE 21e5839ed7SYann Gautier} 22e5839ed7SYann Gautier 23e5839ed7SYann GautierSECTIONS 24e5839ed7SYann Gautier{ 25e5839ed7SYann Gautier /* 26e5839ed7SYann Gautier * TF mapping must conform to ROM code specification. 27e5839ed7SYann Gautier */ 28e5839ed7SYann Gautier .header : { 29e5839ed7SYann Gautier __HEADER_START__ = .; 30e5839ed7SYann Gautier KEEP(*(.header)) 31e5839ed7SYann Gautier . = ALIGN(4); 32e5839ed7SYann Gautier __HEADER_END__ = .; 33e5839ed7SYann Gautier } >HEADER 34e5839ed7SYann Gautier 35e5839ed7SYann Gautier . = STM32MP_BINARY_BASE; 3667788359SYann Gautier .data : { 37e5839ed7SYann Gautier . = ALIGN(PAGE_SIZE); 38e5839ed7SYann Gautier __DATA_START__ = .; 3967788359SYann Gautier FILL(0); 40e5839ed7SYann Gautier 41e5839ed7SYann Gautier /* 42e5839ed7SYann Gautier * dtb. 43e5839ed7SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 44e5839ed7SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 45e5839ed7SYann Gautier */ 46*43560d8eSYann Gautier . = ABSOLUTE( STM32MP_BL2_DTB_BASE ); 47e5839ed7SYann Gautier __DTB_IMAGE_START__ = .; 48e5839ed7SYann Gautier *(.dtb_image*) 49e5839ed7SYann Gautier __DTB_IMAGE_END__ = .; 50e5839ed7SYann Gautier 51e5839ed7SYann Gautier /* 52e5839ed7SYann Gautier * bl2. 53e5839ed7SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 54e5839ed7SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 55e5839ed7SYann Gautier */ 56e5839ed7SYann Gautier#if SEPARATE_CODE_AND_RODATA 57*43560d8eSYann Gautier . = ABSOLUTE( STM32MP_BL2_RO_BASE ); 58e5839ed7SYann Gautier#else 59*43560d8eSYann Gautier . = ABSOLUTE( STM32MP_BL2_BASE ); 60e5839ed7SYann Gautier#endif 61e5839ed7SYann Gautier __BL2_IMAGE_START__ = .; 62e5839ed7SYann Gautier *(.bl2_image*) 63e5839ed7SYann Gautier __BL2_IMAGE_END__ = .; 64e5839ed7SYann Gautier 65e5839ed7SYann Gautier __DATA_END__ = .; 66e5839ed7SYann Gautier } >RAM 67e5839ed7SYann Gautier 68e5839ed7SYann Gautier __TF_END__ = .; 69e5839ed7SYann Gautier 70e5839ed7SYann Gautier} 71e5839ed7SYann Gautier#endif /* STM32MP2_LD_S */ 72