1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <drivers/st/stm32_iwdg.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARCPN_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 24 #define BOARD_ID_VARFG_SHIFT 4 25 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 26 27 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 28 BOARD_ID_BOARD_NB_SHIFT) 29 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 30 BOARD_ID_VARCPN_SHIFT) 31 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 32 BOARD_ID_REVISION_SHIFT) 33 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 34 BOARD_ID_VARFG_SHIFT) 35 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 36 37 #if defined(IMAGE_BL2) 38 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 39 STM32MP_SYSRAM_SIZE, \ 40 MT_MEMORY | \ 41 MT_RW | \ 42 MT_SECURE | \ 43 MT_EXECUTE_NEVER) 44 #elif defined(IMAGE_BL32) 45 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 46 STM32MP_SEC_SYSRAM_SIZE, \ 47 MT_MEMORY | \ 48 MT_RW | \ 49 MT_SECURE | \ 50 MT_EXECUTE_NEVER) 51 52 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 53 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 54 STM32MP_NS_SYSRAM_SIZE, \ 55 MT_DEVICE | \ 56 MT_RW | \ 57 MT_NS | \ 58 MT_EXECUTE_NEVER) 59 #endif 60 61 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 62 STM32MP1_DEVICE1_SIZE, \ 63 MT_DEVICE | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 68 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 69 STM32MP1_DEVICE2_SIZE, \ 70 MT_DEVICE | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 #if defined(IMAGE_BL2) 76 static const mmap_region_t stm32mp1_mmap[] = { 77 MAP_SEC_SYSRAM, 78 MAP_DEVICE1, 79 MAP_DEVICE2, 80 {0} 81 }; 82 #endif 83 #if defined(IMAGE_BL32) 84 static const mmap_region_t stm32mp1_mmap[] = { 85 MAP_SEC_SYSRAM, 86 MAP_NS_SYSRAM, 87 MAP_DEVICE1, 88 MAP_DEVICE2, 89 {0} 90 }; 91 #endif 92 93 void configure_mmu(void) 94 { 95 mmap_add(stm32mp1_mmap); 96 init_xlat_tables(); 97 98 enable_mmu_svc_mon(0); 99 } 100 101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 102 { 103 if (bank == GPIO_BANK_Z) { 104 return GPIOZ_BASE; 105 } 106 107 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 108 109 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 110 } 111 112 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 113 { 114 if (bank == GPIO_BANK_Z) { 115 return 0; 116 } 117 118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 119 120 return bank * GPIO_BANK_OFFSET; 121 } 122 123 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 124 { 125 if (bank == GPIO_BANK_Z) { 126 return GPIOZ; 127 } 128 129 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 130 131 return GPIOA + (bank - GPIO_BANK_A); 132 } 133 134 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 135 { 136 switch (bank) { 137 case GPIO_BANK_A: 138 case GPIO_BANK_B: 139 case GPIO_BANK_C: 140 case GPIO_BANK_D: 141 case GPIO_BANK_E: 142 case GPIO_BANK_F: 143 case GPIO_BANK_G: 144 case GPIO_BANK_H: 145 case GPIO_BANK_I: 146 case GPIO_BANK_J: 147 case GPIO_BANK_K: 148 return fdt_path_offset(fdt, "/soc/pin-controller"); 149 case GPIO_BANK_Z: 150 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 151 default: 152 panic(); 153 } 154 } 155 156 static int get_part_number(uint32_t *part_nb) 157 { 158 uint32_t part_number; 159 uint32_t dev_id; 160 161 assert(part_nb != NULL); 162 163 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 164 return -1; 165 } 166 167 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 168 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 169 return -1; 170 } 171 172 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 173 PART_NUMBER_OTP_PART_SHIFT; 174 175 *part_nb = part_number | (dev_id << 16); 176 177 return 0; 178 } 179 180 static int get_cpu_package(uint32_t *cpu_package) 181 { 182 uint32_t package; 183 184 assert(cpu_package != NULL); 185 186 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 187 ERROR("BSEC: PACKAGE_OTP Error\n"); 188 return -1; 189 } 190 191 *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> 192 PACKAGE_OTP_PKG_SHIFT; 193 194 return 0; 195 } 196 197 void stm32mp_print_cpuinfo(void) 198 { 199 const char *cpu_s, *cpu_r, *pkg; 200 uint32_t part_number; 201 uint32_t cpu_package; 202 uint32_t chip_dev_id; 203 int ret; 204 205 /* MPUs Part Numbers */ 206 ret = get_part_number(&part_number); 207 if (ret < 0) { 208 WARN("Cannot get part number\n"); 209 return; 210 } 211 212 switch (part_number) { 213 case STM32MP157C_PART_NB: 214 cpu_s = "157C"; 215 break; 216 case STM32MP157A_PART_NB: 217 cpu_s = "157A"; 218 break; 219 case STM32MP153C_PART_NB: 220 cpu_s = "153C"; 221 break; 222 case STM32MP153A_PART_NB: 223 cpu_s = "153A"; 224 break; 225 case STM32MP151C_PART_NB: 226 cpu_s = "151C"; 227 break; 228 case STM32MP151A_PART_NB: 229 cpu_s = "151A"; 230 break; 231 case STM32MP157F_PART_NB: 232 cpu_s = "157F"; 233 break; 234 case STM32MP157D_PART_NB: 235 cpu_s = "157D"; 236 break; 237 case STM32MP153F_PART_NB: 238 cpu_s = "153F"; 239 break; 240 case STM32MP153D_PART_NB: 241 cpu_s = "153D"; 242 break; 243 case STM32MP151F_PART_NB: 244 cpu_s = "151F"; 245 break; 246 case STM32MP151D_PART_NB: 247 cpu_s = "151D"; 248 break; 249 default: 250 cpu_s = "????"; 251 break; 252 } 253 254 /* Package */ 255 ret = get_cpu_package(&cpu_package); 256 if (ret < 0) { 257 WARN("Cannot get CPU package\n"); 258 return; 259 } 260 261 switch (cpu_package) { 262 case PKG_AA_LFBGA448: 263 pkg = "AA"; 264 break; 265 case PKG_AB_LFBGA354: 266 pkg = "AB"; 267 break; 268 case PKG_AC_TFBGA361: 269 pkg = "AC"; 270 break; 271 case PKG_AD_TFBGA257: 272 pkg = "AD"; 273 break; 274 default: 275 pkg = "??"; 276 break; 277 } 278 279 /* REVISION */ 280 ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); 281 if (ret < 0) { 282 WARN("Cannot get CPU version\n"); 283 return; 284 } 285 286 switch (chip_dev_id) { 287 case STM32MP1_REV_B: 288 cpu_r = "B"; 289 break; 290 case STM32MP1_REV_Z: 291 cpu_r = "Z"; 292 break; 293 default: 294 cpu_r = "?"; 295 break; 296 } 297 298 NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); 299 } 300 301 void stm32mp_print_boardinfo(void) 302 { 303 uint32_t board_id; 304 uint32_t board_otp; 305 int bsec_node, bsec_board_id_node; 306 void *fdt; 307 const fdt32_t *cuint; 308 309 if (fdt_get_address(&fdt) == 0) { 310 panic(); 311 } 312 313 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 314 if (bsec_node < 0) { 315 return; 316 } 317 318 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 319 if (bsec_board_id_node <= 0) { 320 return; 321 } 322 323 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 324 if (cuint == NULL) { 325 panic(); 326 } 327 328 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 329 330 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 331 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 332 return; 333 } 334 335 if (board_id != 0U) { 336 char rev[2]; 337 338 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 339 rev[1] = '\0'; 340 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 341 BOARD_ID2NB(board_id), 342 BOARD_ID2VARCPN(board_id), 343 BOARD_ID2VARFG(board_id), 344 rev, 345 BOARD_ID2BOM(board_id)); 346 } 347 } 348 349 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 350 bool stm32mp_is_single_core(void) 351 { 352 uint32_t part_number; 353 354 if (get_part_number(&part_number) < 0) { 355 ERROR("Invalid part number, assume single core chip"); 356 return true; 357 } 358 359 switch (part_number) { 360 case STM32MP151A_PART_NB: 361 case STM32MP151C_PART_NB: 362 case STM32MP151D_PART_NB: 363 case STM32MP151F_PART_NB: 364 return true; 365 366 default: 367 return false; 368 } 369 } 370 371 /* Return true when device is in closed state */ 372 bool stm32mp_is_closed_device(void) 373 { 374 uint32_t value; 375 376 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 377 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 378 return true; 379 } 380 381 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 382 } 383 384 uint32_t stm32_iwdg_get_instance(uintptr_t base) 385 { 386 switch (base) { 387 case IWDG1_BASE: 388 return IWDG1_INST; 389 case IWDG2_BASE: 390 return IWDG2_INST; 391 default: 392 panic(); 393 } 394 } 395 396 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 397 { 398 uint32_t iwdg_cfg = 0U; 399 uint32_t otp_value; 400 401 #if defined(IMAGE_BL2) 402 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 403 panic(); 404 } 405 #endif 406 407 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 408 panic(); 409 } 410 411 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 412 iwdg_cfg |= IWDG_HW_ENABLED; 413 } 414 415 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 416 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 417 } 418 419 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 420 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 421 } 422 423 return iwdg_cfg; 424 } 425 426 #if defined(IMAGE_BL2) 427 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 428 { 429 uint32_t otp; 430 uint32_t result; 431 432 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 433 panic(); 434 } 435 436 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 437 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 438 } 439 440 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 441 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 442 } 443 444 result = bsec_write_otp(otp, HW2_OTP); 445 if (result != BSEC_OK) { 446 return result; 447 } 448 449 /* Sticky lock OTP_IWDG (read and write) */ 450 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 451 !bsec_write_sw_lock(HW2_OTP, 1U)) { 452 return BSEC_LOCK_FAIL; 453 } 454 455 return BSEC_OK; 456 } 457 #endif 458 459 /* Get the non-secure DDR size */ 460 uint32_t stm32mp_get_ddr_ns_size(void) 461 { 462 static uint32_t ddr_ns_size; 463 uint32_t ddr_size; 464 465 if (ddr_ns_size != 0U) { 466 return ddr_ns_size; 467 } 468 469 ddr_size = dt_get_ddr_size(); 470 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 471 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 472 panic(); 473 } 474 475 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 476 477 return ddr_ns_size; 478 } 479