1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 41 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 42 #define TAMP_BOOT_MODE_ITF_SHIFT 8 43 44 #define TAMP_BOOT_COUNTER_REG_ID U(21) 45 46 #if defined(IMAGE_BL2) 47 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 48 STM32MP_SYSRAM_SIZE, \ 49 MT_MEMORY | \ 50 MT_RW | \ 51 MT_SECURE | \ 52 MT_EXECUTE_NEVER) 53 #elif defined(IMAGE_BL32) 54 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 55 STM32MP_SEC_SYSRAM_SIZE, \ 56 MT_MEMORY | \ 57 MT_RW | \ 58 MT_SECURE | \ 59 MT_EXECUTE_NEVER) 60 61 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 62 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 63 STM32MP_NS_SYSRAM_SIZE, \ 64 MT_DEVICE | \ 65 MT_RW | \ 66 MT_NS | \ 67 MT_EXECUTE_NEVER) 68 #endif 69 70 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 71 STM32MP1_DEVICE1_SIZE, \ 72 MT_DEVICE | \ 73 MT_RW | \ 74 MT_SECURE | \ 75 MT_EXECUTE_NEVER) 76 77 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 78 STM32MP1_DEVICE2_SIZE, \ 79 MT_DEVICE | \ 80 MT_RW | \ 81 MT_SECURE | \ 82 MT_EXECUTE_NEVER) 83 84 #if defined(IMAGE_BL2) 85 static const mmap_region_t stm32mp1_mmap[] = { 86 MAP_SEC_SYSRAM, 87 MAP_DEVICE1, 88 #if STM32MP_RAW_NAND 89 MAP_DEVICE2, 90 #endif 91 {0} 92 }; 93 #endif 94 #if defined(IMAGE_BL32) 95 static const mmap_region_t stm32mp1_mmap[] = { 96 MAP_SEC_SYSRAM, 97 MAP_NS_SYSRAM, 98 MAP_DEVICE1, 99 MAP_DEVICE2, 100 {0} 101 }; 102 #endif 103 104 void configure_mmu(void) 105 { 106 mmap_add(stm32mp1_mmap); 107 init_xlat_tables(); 108 109 enable_mmu_svc_mon(0); 110 } 111 112 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 113 { 114 if (bank == GPIO_BANK_Z) { 115 return GPIOZ_BASE; 116 } 117 118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 119 120 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 121 } 122 123 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 124 { 125 if (bank == GPIO_BANK_Z) { 126 return 0; 127 } 128 129 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 130 131 return bank * GPIO_BANK_OFFSET; 132 } 133 134 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 135 { 136 if (bank == GPIO_BANK_Z) { 137 return true; 138 } 139 140 return false; 141 } 142 143 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 144 { 145 if (bank == GPIO_BANK_Z) { 146 return GPIOZ; 147 } 148 149 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 150 151 return GPIOA + (bank - GPIO_BANK_A); 152 } 153 154 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 155 { 156 switch (bank) { 157 case GPIO_BANK_A: 158 case GPIO_BANK_B: 159 case GPIO_BANK_C: 160 case GPIO_BANK_D: 161 case GPIO_BANK_E: 162 case GPIO_BANK_F: 163 case GPIO_BANK_G: 164 case GPIO_BANK_H: 165 case GPIO_BANK_I: 166 case GPIO_BANK_J: 167 case GPIO_BANK_K: 168 return fdt_path_offset(fdt, "/soc/pin-controller"); 169 case GPIO_BANK_Z: 170 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 171 default: 172 panic(); 173 } 174 } 175 176 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 177 /* 178 * UART Management 179 */ 180 static const uintptr_t stm32mp1_uart_addresses[8] = { 181 USART1_BASE, 182 USART2_BASE, 183 USART3_BASE, 184 UART4_BASE, 185 UART5_BASE, 186 USART6_BASE, 187 UART7_BASE, 188 UART8_BASE, 189 }; 190 191 uintptr_t get_uart_address(uint32_t instance_nb) 192 { 193 if ((instance_nb == 0U) || 194 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 195 return 0U; 196 } 197 198 return stm32mp1_uart_addresses[instance_nb - 1U]; 199 } 200 #endif 201 202 #if STM32MP_USB_PROGRAMMER 203 struct gpio_bank_pin_list { 204 uint32_t bank; 205 uint32_t pin; 206 }; 207 208 static const struct gpio_bank_pin_list gpio_list[] = { 209 { /* USART2_RX: GPIOA3 */ 210 .bank = 0U, 211 .pin = 3U, 212 }, 213 { /* USART3_RX: GPIOB12 */ 214 .bank = 1U, 215 .pin = 12U, 216 }, 217 { /* UART4_RX: GPIOB2 */ 218 .bank = 1U, 219 .pin = 2U, 220 }, 221 { /* UART5_RX: GPIOB4 */ 222 .bank = 1U, 223 .pin = 5U, 224 }, 225 { /* USART6_RX: GPIOC7 */ 226 .bank = 2U, 227 .pin = 7U, 228 }, 229 { /* UART7_RX: GPIOF6 */ 230 .bank = 5U, 231 .pin = 6U, 232 }, 233 { /* UART8_RX: GPIOE0 */ 234 .bank = 4U, 235 .pin = 0U, 236 }, 237 }; 238 239 void stm32mp1_deconfigure_uart_pins(void) 240 { 241 size_t i; 242 243 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 244 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 245 } 246 } 247 #endif 248 249 uint32_t stm32mp_get_chip_version(void) 250 { 251 uint32_t version = 0U; 252 253 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 254 INFO("Cannot get CPU version, debug disabled\n"); 255 return 0U; 256 } 257 258 return version; 259 } 260 261 uint32_t stm32mp_get_chip_dev_id(void) 262 { 263 uint32_t dev_id; 264 265 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 266 INFO("Use default chip ID, debug disabled\n"); 267 dev_id = STM32MP1_CHIP_ID; 268 } 269 270 return dev_id; 271 } 272 273 static uint32_t get_part_number(void) 274 { 275 static uint32_t part_number; 276 277 if (part_number != 0U) { 278 return part_number; 279 } 280 281 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 282 panic(); 283 } 284 285 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 286 PART_NUMBER_OTP_PART_SHIFT; 287 288 part_number |= stm32mp_get_chip_dev_id() << 16; 289 290 return part_number; 291 } 292 293 static uint32_t get_cpu_package(void) 294 { 295 uint32_t package; 296 297 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 298 panic(); 299 } 300 301 package = (package & PACKAGE_OTP_PKG_MASK) >> 302 PACKAGE_OTP_PKG_SHIFT; 303 304 return package; 305 } 306 307 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 308 { 309 char *cpu_s, *cpu_r, *pkg; 310 311 /* MPUs Part Numbers */ 312 switch (get_part_number()) { 313 case STM32MP157C_PART_NB: 314 cpu_s = "157C"; 315 break; 316 case STM32MP157A_PART_NB: 317 cpu_s = "157A"; 318 break; 319 case STM32MP153C_PART_NB: 320 cpu_s = "153C"; 321 break; 322 case STM32MP153A_PART_NB: 323 cpu_s = "153A"; 324 break; 325 case STM32MP151C_PART_NB: 326 cpu_s = "151C"; 327 break; 328 case STM32MP151A_PART_NB: 329 cpu_s = "151A"; 330 break; 331 case STM32MP157F_PART_NB: 332 cpu_s = "157F"; 333 break; 334 case STM32MP157D_PART_NB: 335 cpu_s = "157D"; 336 break; 337 case STM32MP153F_PART_NB: 338 cpu_s = "153F"; 339 break; 340 case STM32MP153D_PART_NB: 341 cpu_s = "153D"; 342 break; 343 case STM32MP151F_PART_NB: 344 cpu_s = "151F"; 345 break; 346 case STM32MP151D_PART_NB: 347 cpu_s = "151D"; 348 break; 349 default: 350 cpu_s = "????"; 351 break; 352 } 353 354 /* Package */ 355 switch (get_cpu_package()) { 356 case PKG_AA_LFBGA448: 357 pkg = "AA"; 358 break; 359 case PKG_AB_LFBGA354: 360 pkg = "AB"; 361 break; 362 case PKG_AC_TFBGA361: 363 pkg = "AC"; 364 break; 365 case PKG_AD_TFBGA257: 366 pkg = "AD"; 367 break; 368 default: 369 pkg = "??"; 370 break; 371 } 372 373 /* REVISION */ 374 switch (stm32mp_get_chip_version()) { 375 case STM32MP1_REV_B: 376 cpu_r = "B"; 377 break; 378 case STM32MP1_REV_Z: 379 cpu_r = "Z"; 380 break; 381 default: 382 cpu_r = "?"; 383 break; 384 } 385 386 snprintf(name, STM32_SOC_NAME_SIZE, 387 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 388 } 389 390 void stm32mp_print_cpuinfo(void) 391 { 392 char name[STM32_SOC_NAME_SIZE]; 393 394 stm32mp_get_soc_name(name); 395 NOTICE("CPU: %s\n", name); 396 } 397 398 void stm32mp_print_boardinfo(void) 399 { 400 uint32_t board_id = 0; 401 402 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 403 return; 404 } 405 406 if (board_id != 0U) { 407 char rev[2]; 408 409 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 410 rev[1] = '\0'; 411 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 412 BOARD_ID2NB(board_id), 413 BOARD_ID2VARCPN(board_id), 414 BOARD_ID2VARFG(board_id), 415 rev, 416 BOARD_ID2BOM(board_id)); 417 } 418 } 419 420 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 421 bool stm32mp_is_single_core(void) 422 { 423 bool single_core = false; 424 425 switch (get_part_number()) { 426 case STM32MP151A_PART_NB: 427 case STM32MP151C_PART_NB: 428 case STM32MP151D_PART_NB: 429 case STM32MP151F_PART_NB: 430 single_core = true; 431 break; 432 default: 433 break; 434 } 435 436 return single_core; 437 } 438 439 /* Return true when device is in closed state */ 440 bool stm32mp_is_closed_device(void) 441 { 442 uint32_t value; 443 444 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 445 return true; 446 } 447 448 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 449 } 450 451 /* Return true when device supports secure boot */ 452 bool stm32mp_is_auth_supported(void) 453 { 454 bool supported = false; 455 456 switch (get_part_number()) { 457 case STM32MP151C_PART_NB: 458 case STM32MP151F_PART_NB: 459 case STM32MP153C_PART_NB: 460 case STM32MP153F_PART_NB: 461 case STM32MP157C_PART_NB: 462 case STM32MP157F_PART_NB: 463 supported = true; 464 break; 465 default: 466 break; 467 } 468 469 return supported; 470 } 471 472 uint32_t stm32_iwdg_get_instance(uintptr_t base) 473 { 474 switch (base) { 475 case IWDG1_BASE: 476 return IWDG1_INST; 477 case IWDG2_BASE: 478 return IWDG2_INST; 479 default: 480 panic(); 481 } 482 } 483 484 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 485 { 486 uint32_t iwdg_cfg = 0U; 487 uint32_t otp_value; 488 489 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 490 panic(); 491 } 492 493 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 494 iwdg_cfg |= IWDG_HW_ENABLED; 495 } 496 497 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 498 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 499 } 500 501 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 502 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 503 } 504 505 return iwdg_cfg; 506 } 507 508 #if defined(IMAGE_BL2) 509 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 510 { 511 uint32_t otp_value; 512 uint32_t otp; 513 uint32_t result; 514 515 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 516 panic(); 517 } 518 519 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 520 panic(); 521 } 522 523 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 524 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 525 } 526 527 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 528 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 529 } 530 531 result = bsec_write_otp(otp_value, otp); 532 if (result != BSEC_OK) { 533 return result; 534 } 535 536 /* Sticky lock OTP_IWDG (read and write) */ 537 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 538 (bsec_set_sw_lock(otp) != BSEC_OK)) { 539 return BSEC_LOCK_FAIL; 540 } 541 542 return BSEC_OK; 543 } 544 #endif 545 546 #if STM32MP_USE_STM32IMAGE 547 /* Get the non-secure DDR size */ 548 uint32_t stm32mp_get_ddr_ns_size(void) 549 { 550 static uint32_t ddr_ns_size; 551 uint32_t ddr_size; 552 553 if (ddr_ns_size != 0U) { 554 return ddr_ns_size; 555 } 556 557 ddr_size = dt_get_ddr_size(); 558 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 559 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 560 panic(); 561 } 562 563 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 564 565 return ddr_ns_size; 566 } 567 #endif /* STM32MP_USE_STM32IMAGE */ 568 569 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 570 { 571 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 572 573 clk_enable(RTCAPB); 574 575 mmio_clrsetbits_32(bkpr_itf_idx, 576 TAMP_BOOT_MODE_ITF_MASK, 577 ((interface << 4) | (instance & 0xFU)) << 578 TAMP_BOOT_MODE_ITF_SHIFT); 579 580 clk_disable(RTCAPB); 581 } 582 583 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 584 { 585 static uint32_t itf; 586 587 if (itf == 0U) { 588 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 589 590 clk_enable(RTCAPB); 591 592 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 593 TAMP_BOOT_MODE_ITF_SHIFT; 594 595 clk_disable(RTCAPB); 596 } 597 598 *interface = itf >> 4; 599 *instance = itf & 0xFU; 600 } 601 602 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 603 void stm32mp1_fwu_set_boot_idx(void) 604 { 605 clk_enable(RTCAPB); 606 mmio_write_32(tamp_bkpr(TAMP_BOOT_COUNTER_REG_ID), 607 plat_fwu_get_boot_idx()); 608 clk_disable(RTCAPB); 609 } 610 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 611