1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #if STM32MP13 41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 42 #endif 43 #if STM32MP15 44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 45 #endif 46 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 47 #define TAMP_BOOT_MODE_ITF_SHIFT 8 48 49 #define TAMP_BOOT_COUNTER_REG_ID U(21) 50 51 #if defined(IMAGE_BL2) 52 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 53 STM32MP_SYSRAM_SIZE, \ 54 MT_MEMORY | \ 55 MT_RW | \ 56 MT_SECURE | \ 57 MT_EXECUTE_NEVER) 58 #elif defined(IMAGE_BL32) 59 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 60 STM32MP_SEC_SYSRAM_SIZE, \ 61 MT_MEMORY | \ 62 MT_RW | \ 63 MT_SECURE | \ 64 MT_EXECUTE_NEVER) 65 66 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 67 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 68 STM32MP_NS_SYSRAM_SIZE, \ 69 MT_DEVICE | \ 70 MT_RW | \ 71 MT_NS | \ 72 MT_EXECUTE_NEVER) 73 #endif 74 75 #if STM32MP13 76 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 77 SRAMS_SIZE_2MB_ALIGNED, \ 78 MT_MEMORY | \ 79 MT_RW | \ 80 MT_SECURE | \ 81 MT_EXECUTE_NEVER) 82 #endif 83 84 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 85 STM32MP1_DEVICE1_SIZE, \ 86 MT_DEVICE | \ 87 MT_RW | \ 88 MT_SECURE | \ 89 MT_EXECUTE_NEVER) 90 91 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 92 STM32MP1_DEVICE2_SIZE, \ 93 MT_DEVICE | \ 94 MT_RW | \ 95 MT_SECURE | \ 96 MT_EXECUTE_NEVER) 97 98 #if defined(IMAGE_BL2) 99 static const mmap_region_t stm32mp1_mmap[] = { 100 MAP_SEC_SYSRAM, 101 #if STM32MP13 102 MAP_SRAM_ALL, 103 #endif 104 MAP_DEVICE1, 105 #if STM32MP_RAW_NAND 106 MAP_DEVICE2, 107 #endif 108 {0} 109 }; 110 #endif 111 #if defined(IMAGE_BL32) 112 static const mmap_region_t stm32mp1_mmap[] = { 113 MAP_SEC_SYSRAM, 114 MAP_NS_SYSRAM, 115 MAP_DEVICE1, 116 MAP_DEVICE2, 117 {0} 118 }; 119 #endif 120 121 void configure_mmu(void) 122 { 123 mmap_add(stm32mp1_mmap); 124 init_xlat_tables(); 125 126 enable_mmu_svc_mon(0); 127 } 128 129 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 130 { 131 #if STM32MP13 132 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 133 #endif 134 #if STM32MP15 135 if (bank == GPIO_BANK_Z) { 136 return GPIOZ_BASE; 137 } 138 139 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 140 #endif 141 142 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 143 } 144 145 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 146 { 147 #if STM32MP13 148 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 149 #endif 150 #if STM32MP15 151 if (bank == GPIO_BANK_Z) { 152 return 0; 153 } 154 155 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 156 #endif 157 158 return bank * GPIO_BANK_OFFSET; 159 } 160 161 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 162 { 163 #if STM32MP13 164 return true; 165 #endif 166 #if STM32MP15 167 if (bank == GPIO_BANK_Z) { 168 return true; 169 } 170 171 return false; 172 #endif 173 } 174 175 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 176 { 177 #if STM32MP13 178 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 179 #endif 180 #if STM32MP15 181 if (bank == GPIO_BANK_Z) { 182 return GPIOZ; 183 } 184 185 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 186 #endif 187 188 return GPIOA + (bank - GPIO_BANK_A); 189 } 190 191 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 192 { 193 switch (bank) { 194 case GPIO_BANK_A: 195 case GPIO_BANK_B: 196 case GPIO_BANK_C: 197 case GPIO_BANK_D: 198 case GPIO_BANK_E: 199 case GPIO_BANK_F: 200 case GPIO_BANK_G: 201 case GPIO_BANK_H: 202 case GPIO_BANK_I: 203 #if STM32MP15 204 case GPIO_BANK_J: 205 case GPIO_BANK_K: 206 #endif 207 return fdt_path_offset(fdt, "/soc/pin-controller"); 208 #if STM32MP15 209 case GPIO_BANK_Z: 210 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 211 #endif 212 default: 213 panic(); 214 } 215 } 216 217 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 218 /* 219 * UART Management 220 */ 221 static const uintptr_t stm32mp1_uart_addresses[8] = { 222 USART1_BASE, 223 USART2_BASE, 224 USART3_BASE, 225 UART4_BASE, 226 UART5_BASE, 227 USART6_BASE, 228 UART7_BASE, 229 UART8_BASE, 230 }; 231 232 uintptr_t get_uart_address(uint32_t instance_nb) 233 { 234 if ((instance_nb == 0U) || 235 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 236 return 0U; 237 } 238 239 return stm32mp1_uart_addresses[instance_nb - 1U]; 240 } 241 #endif 242 243 #if STM32MP_USB_PROGRAMMER 244 struct gpio_bank_pin_list { 245 uint32_t bank; 246 uint32_t pin; 247 }; 248 249 static const struct gpio_bank_pin_list gpio_list[] = { 250 { /* USART2_RX: GPIOA3 */ 251 .bank = 0U, 252 .pin = 3U, 253 }, 254 { /* USART3_RX: GPIOB12 */ 255 .bank = 1U, 256 .pin = 12U, 257 }, 258 { /* UART4_RX: GPIOB2 */ 259 .bank = 1U, 260 .pin = 2U, 261 }, 262 { /* UART5_RX: GPIOB4 */ 263 .bank = 1U, 264 .pin = 5U, 265 }, 266 { /* USART6_RX: GPIOC7 */ 267 .bank = 2U, 268 .pin = 7U, 269 }, 270 { /* UART7_RX: GPIOF6 */ 271 .bank = 5U, 272 .pin = 6U, 273 }, 274 { /* UART8_RX: GPIOE0 */ 275 .bank = 4U, 276 .pin = 0U, 277 }, 278 }; 279 280 void stm32mp1_deconfigure_uart_pins(void) 281 { 282 size_t i; 283 284 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 285 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 286 } 287 } 288 #endif 289 290 uint32_t stm32mp_get_chip_version(void) 291 { 292 uint32_t version = 0U; 293 294 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 295 INFO("Cannot get CPU version, debug disabled\n"); 296 return 0U; 297 } 298 299 return version; 300 } 301 302 uint32_t stm32mp_get_chip_dev_id(void) 303 { 304 uint32_t dev_id; 305 306 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 307 INFO("Use default chip ID, debug disabled\n"); 308 dev_id = STM32MP1_CHIP_ID; 309 } 310 311 return dev_id; 312 } 313 314 static uint32_t get_part_number(void) 315 { 316 static uint32_t part_number; 317 318 if (part_number != 0U) { 319 return part_number; 320 } 321 322 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 323 panic(); 324 } 325 326 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 327 PART_NUMBER_OTP_PART_SHIFT; 328 329 part_number |= stm32mp_get_chip_dev_id() << 16; 330 331 return part_number; 332 } 333 334 #if STM32MP15 335 static uint32_t get_cpu_package(void) 336 { 337 uint32_t package; 338 339 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 340 panic(); 341 } 342 343 package = (package & PACKAGE_OTP_PKG_MASK) >> 344 PACKAGE_OTP_PKG_SHIFT; 345 346 return package; 347 } 348 #endif 349 350 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 351 { 352 char *cpu_s, *cpu_r, *pkg; 353 354 /* MPUs Part Numbers */ 355 switch (get_part_number()) { 356 #if STM32MP13 357 case STM32MP135F_PART_NB: 358 cpu_s = "135F"; 359 break; 360 case STM32MP135D_PART_NB: 361 cpu_s = "135D"; 362 break; 363 case STM32MP135C_PART_NB: 364 cpu_s = "135C"; 365 break; 366 case STM32MP135A_PART_NB: 367 cpu_s = "135A"; 368 break; 369 case STM32MP133F_PART_NB: 370 cpu_s = "133F"; 371 break; 372 case STM32MP133D_PART_NB: 373 cpu_s = "133D"; 374 break; 375 case STM32MP133C_PART_NB: 376 cpu_s = "133C"; 377 break; 378 case STM32MP133A_PART_NB: 379 cpu_s = "133A"; 380 break; 381 case STM32MP131F_PART_NB: 382 cpu_s = "131F"; 383 break; 384 case STM32MP131D_PART_NB: 385 cpu_s = "131D"; 386 break; 387 case STM32MP131C_PART_NB: 388 cpu_s = "131C"; 389 break; 390 case STM32MP131A_PART_NB: 391 cpu_s = "131A"; 392 break; 393 #endif 394 #if STM32MP15 395 case STM32MP157C_PART_NB: 396 cpu_s = "157C"; 397 break; 398 case STM32MP157A_PART_NB: 399 cpu_s = "157A"; 400 break; 401 case STM32MP153C_PART_NB: 402 cpu_s = "153C"; 403 break; 404 case STM32MP153A_PART_NB: 405 cpu_s = "153A"; 406 break; 407 case STM32MP151C_PART_NB: 408 cpu_s = "151C"; 409 break; 410 case STM32MP151A_PART_NB: 411 cpu_s = "151A"; 412 break; 413 case STM32MP157F_PART_NB: 414 cpu_s = "157F"; 415 break; 416 case STM32MP157D_PART_NB: 417 cpu_s = "157D"; 418 break; 419 case STM32MP153F_PART_NB: 420 cpu_s = "153F"; 421 break; 422 case STM32MP153D_PART_NB: 423 cpu_s = "153D"; 424 break; 425 case STM32MP151F_PART_NB: 426 cpu_s = "151F"; 427 break; 428 case STM32MP151D_PART_NB: 429 cpu_s = "151D"; 430 break; 431 #endif 432 default: 433 cpu_s = "????"; 434 break; 435 } 436 437 /* Package */ 438 #if STM32MP13 439 /* On STM32MP13, package is not present in OTP */ 440 pkg = ""; 441 #endif 442 #if STM32MP15 443 switch (get_cpu_package()) { 444 case PKG_AA_LFBGA448: 445 pkg = "AA"; 446 break; 447 case PKG_AB_LFBGA354: 448 pkg = "AB"; 449 break; 450 case PKG_AC_TFBGA361: 451 pkg = "AC"; 452 break; 453 case PKG_AD_TFBGA257: 454 pkg = "AD"; 455 break; 456 default: 457 pkg = "??"; 458 break; 459 } 460 #endif 461 462 /* REVISION */ 463 switch (stm32mp_get_chip_version()) { 464 case STM32MP1_REV_B: 465 cpu_r = "B"; 466 break; 467 case STM32MP1_REV_Z: 468 cpu_r = "Z"; 469 break; 470 default: 471 cpu_r = "?"; 472 break; 473 } 474 475 snprintf(name, STM32_SOC_NAME_SIZE, 476 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 477 } 478 479 void stm32mp_print_cpuinfo(void) 480 { 481 char name[STM32_SOC_NAME_SIZE]; 482 483 stm32mp_get_soc_name(name); 484 NOTICE("CPU: %s\n", name); 485 } 486 487 void stm32mp_print_boardinfo(void) 488 { 489 uint32_t board_id = 0; 490 491 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 492 return; 493 } 494 495 if (board_id != 0U) { 496 char rev[2]; 497 498 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 499 rev[1] = '\0'; 500 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 501 BOARD_ID2NB(board_id), 502 BOARD_ID2VARCPN(board_id), 503 BOARD_ID2VARFG(board_id), 504 rev, 505 BOARD_ID2BOM(board_id)); 506 } 507 } 508 509 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 510 bool stm32mp_is_single_core(void) 511 { 512 #if STM32MP13 513 return true; 514 #endif 515 #if STM32MP15 516 bool single_core = false; 517 518 switch (get_part_number()) { 519 case STM32MP151A_PART_NB: 520 case STM32MP151C_PART_NB: 521 case STM32MP151D_PART_NB: 522 case STM32MP151F_PART_NB: 523 single_core = true; 524 break; 525 default: 526 break; 527 } 528 529 return single_core; 530 #endif 531 } 532 533 /* Return true when device is in closed state */ 534 bool stm32mp_is_closed_device(void) 535 { 536 uint32_t value; 537 538 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 539 return true; 540 } 541 542 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 543 } 544 545 /* Return true when device supports secure boot */ 546 bool stm32mp_is_auth_supported(void) 547 { 548 bool supported = false; 549 550 switch (get_part_number()) { 551 #if STM32MP13 552 case STM32MP131C_PART_NB: 553 case STM32MP131F_PART_NB: 554 case STM32MP133C_PART_NB: 555 case STM32MP133F_PART_NB: 556 case STM32MP135C_PART_NB: 557 case STM32MP135F_PART_NB: 558 #endif 559 #if STM32MP15 560 case STM32MP151C_PART_NB: 561 case STM32MP151F_PART_NB: 562 case STM32MP153C_PART_NB: 563 case STM32MP153F_PART_NB: 564 case STM32MP157C_PART_NB: 565 case STM32MP157F_PART_NB: 566 #endif 567 supported = true; 568 break; 569 default: 570 break; 571 } 572 573 return supported; 574 } 575 576 uint32_t stm32_iwdg_get_instance(uintptr_t base) 577 { 578 switch (base) { 579 case IWDG1_BASE: 580 return IWDG1_INST; 581 case IWDG2_BASE: 582 return IWDG2_INST; 583 default: 584 panic(); 585 } 586 } 587 588 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 589 { 590 uint32_t iwdg_cfg = 0U; 591 uint32_t otp_value; 592 593 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 594 panic(); 595 } 596 597 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 598 iwdg_cfg |= IWDG_HW_ENABLED; 599 } 600 601 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 602 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 603 } 604 605 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 606 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 607 } 608 609 return iwdg_cfg; 610 } 611 612 #if defined(IMAGE_BL2) 613 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 614 { 615 uint32_t otp_value; 616 uint32_t otp; 617 uint32_t result; 618 619 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 620 panic(); 621 } 622 623 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 624 panic(); 625 } 626 627 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 628 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 629 } 630 631 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 632 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 633 } 634 635 result = bsec_write_otp(otp_value, otp); 636 if (result != BSEC_OK) { 637 return result; 638 } 639 640 /* Sticky lock OTP_IWDG (read and write) */ 641 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 642 (bsec_set_sw_lock(otp) != BSEC_OK)) { 643 return BSEC_LOCK_FAIL; 644 } 645 646 return BSEC_OK; 647 } 648 #endif 649 650 #if STM32MP_USE_STM32IMAGE 651 /* Get the non-secure DDR size */ 652 uint32_t stm32mp_get_ddr_ns_size(void) 653 { 654 static uint32_t ddr_ns_size; 655 uint32_t ddr_size; 656 657 if (ddr_ns_size != 0U) { 658 return ddr_ns_size; 659 } 660 661 ddr_size = dt_get_ddr_size(); 662 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 663 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 664 panic(); 665 } 666 667 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 668 669 return ddr_ns_size; 670 } 671 #endif /* STM32MP_USE_STM32IMAGE */ 672 673 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 674 { 675 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 676 677 clk_enable(RTCAPB); 678 679 mmio_clrsetbits_32(bkpr_itf_idx, 680 TAMP_BOOT_MODE_ITF_MASK, 681 ((interface << 4) | (instance & 0xFU)) << 682 TAMP_BOOT_MODE_ITF_SHIFT); 683 684 clk_disable(RTCAPB); 685 } 686 687 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 688 { 689 static uint32_t itf; 690 691 if (itf == 0U) { 692 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 693 694 clk_enable(RTCAPB); 695 696 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 697 TAMP_BOOT_MODE_ITF_SHIFT; 698 699 clk_disable(RTCAPB); 700 } 701 702 *interface = itf >> 4; 703 *instance = itf & 0xFU; 704 } 705 706 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 707 void stm32mp1_fwu_set_boot_idx(void) 708 { 709 clk_enable(RTCAPB); 710 mmio_write_32(tamp_bkpr(TAMP_BOOT_COUNTER_REG_ID), 711 plat_fwu_get_boot_idx()); 712 clk_disable(RTCAPB); 713 } 714 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 715