1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 14 #define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 15 STM32MP_SYSRAM_SIZE, \ 16 MT_MEMORY | \ 17 MT_RW | \ 18 MT_SECURE | \ 19 MT_EXECUTE_NEVER) 20 21 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 22 STM32MP1_DEVICE1_SIZE, \ 23 MT_DEVICE | \ 24 MT_RW | \ 25 MT_SECURE | \ 26 MT_EXECUTE_NEVER) 27 28 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 29 STM32MP1_DEVICE2_SIZE, \ 30 MT_DEVICE | \ 31 MT_RW | \ 32 MT_SECURE | \ 33 MT_EXECUTE_NEVER) 34 35 #if defined(IMAGE_BL2) 36 static const mmap_region_t stm32mp1_mmap[] = { 37 MAP_SRAM, 38 MAP_DEVICE1, 39 MAP_DEVICE2, 40 {0} 41 }; 42 #endif 43 #if defined(IMAGE_BL32) 44 static const mmap_region_t stm32mp1_mmap[] = { 45 MAP_SRAM, 46 MAP_DEVICE1, 47 MAP_DEVICE2, 48 {0} 49 }; 50 #endif 51 52 void configure_mmu(void) 53 { 54 mmap_add(stm32mp1_mmap); 55 init_xlat_tables(); 56 57 enable_mmu_svc_mon(0); 58 } 59 60 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 61 { 62 if (bank == GPIO_BANK_Z) { 63 return GPIOZ; 64 } 65 66 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 67 68 return GPIOA + (bank - GPIO_BANK_A); 69 } 70 71 uint32_t stm32_iwdg_get_instance(uintptr_t base) 72 { 73 switch (base) { 74 case IWDG1_BASE: 75 return IWDG1_INST; 76 case IWDG2_BASE: 77 return IWDG2_INST; 78 default: 79 panic(); 80 } 81 } 82 83 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 84 { 85 uint32_t iwdg_cfg = 0U; 86 uint32_t otp_value; 87 88 #if defined(IMAGE_BL2) 89 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 90 panic(); 91 } 92 #endif 93 94 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 95 panic(); 96 } 97 98 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 99 iwdg_cfg |= IWDG_HW_ENABLED; 100 } 101 102 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 103 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 104 } 105 106 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 107 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 108 } 109 110 return iwdg_cfg; 111 } 112 113 #if defined(IMAGE_BL2) 114 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 115 { 116 uint32_t otp; 117 uint32_t result; 118 119 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 120 panic(); 121 } 122 123 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 124 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 125 } 126 127 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 128 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 129 } 130 131 result = bsec_write_otp(otp, HW2_OTP); 132 if (result != BSEC_OK) { 133 return result; 134 } 135 136 /* Sticky lock OTP_IWDG (read and write) */ 137 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 138 !bsec_write_sw_lock(HW2_OTP, 1U)) { 139 return BSEC_LOCK_FAIL; 140 } 141 142 return BSEC_OK; 143 } 144 #endif 145