1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #if STM32MP13 41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 42 #endif 43 #if STM32MP15 44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 45 #endif 46 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 47 #define TAMP_BOOT_MODE_ITF_SHIFT 8 48 49 /* 50 * Backup register to store fwu update information. 51 * It should be writeable only by secure world, but also readable by non secure 52 * (so it should be in Zone 2). 53 */ 54 #define TAMP_BOOT_FWU_INFO_REG_ID U(10) 55 #define TAMP_BOOT_FWU_INFO_IDX_MSK U(0xF) 56 #define TAMP_BOOT_FWU_INFO_IDX_OFF U(0) 57 #define TAMP_BOOT_FWU_INFO_CNT_MSK U(0xF0) 58 #define TAMP_BOOT_FWU_INFO_CNT_OFF U(4) 59 60 #if defined(IMAGE_BL2) 61 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 62 STM32MP_SYSRAM_SIZE, \ 63 MT_MEMORY | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 #elif defined(IMAGE_BL32) 68 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 69 STM32MP_SEC_SYSRAM_SIZE, \ 70 MT_MEMORY | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 76 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 77 STM32MP_NS_SYSRAM_SIZE, \ 78 MT_DEVICE | \ 79 MT_RW | \ 80 MT_NS | \ 81 MT_EXECUTE_NEVER) 82 #endif 83 84 #if STM32MP13 85 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 86 SRAMS_SIZE_2MB_ALIGNED, \ 87 MT_MEMORY | \ 88 MT_RW | \ 89 MT_SECURE | \ 90 MT_EXECUTE_NEVER) 91 #endif 92 93 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 94 STM32MP1_DEVICE1_SIZE, \ 95 MT_DEVICE | \ 96 MT_RW | \ 97 MT_SECURE | \ 98 MT_EXECUTE_NEVER) 99 100 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 101 STM32MP1_DEVICE2_SIZE, \ 102 MT_DEVICE | \ 103 MT_RW | \ 104 MT_SECURE | \ 105 MT_EXECUTE_NEVER) 106 107 #if defined(IMAGE_BL2) 108 static const mmap_region_t stm32mp1_mmap[] = { 109 MAP_SEC_SYSRAM, 110 #if STM32MP13 111 MAP_SRAM_ALL, 112 #endif 113 MAP_DEVICE1, 114 #if STM32MP_RAW_NAND 115 MAP_DEVICE2, 116 #endif 117 {0} 118 }; 119 #endif 120 #if defined(IMAGE_BL32) 121 static const mmap_region_t stm32mp1_mmap[] = { 122 MAP_SEC_SYSRAM, 123 MAP_NS_SYSRAM, 124 MAP_DEVICE1, 125 MAP_DEVICE2, 126 {0} 127 }; 128 #endif 129 130 void configure_mmu(void) 131 { 132 mmap_add(stm32mp1_mmap); 133 init_xlat_tables(); 134 135 enable_mmu_svc_mon(0); 136 } 137 138 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 139 { 140 #if STM32MP13 141 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 142 #endif 143 #if STM32MP15 144 if (bank == GPIO_BANK_Z) { 145 return GPIOZ_BASE; 146 } 147 148 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 149 #endif 150 151 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 152 } 153 154 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 155 { 156 #if STM32MP13 157 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 158 #endif 159 #if STM32MP15 160 if (bank == GPIO_BANK_Z) { 161 return 0; 162 } 163 164 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 165 #endif 166 167 return bank * GPIO_BANK_OFFSET; 168 } 169 170 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 171 { 172 #if STM32MP13 173 return true; 174 #endif 175 #if STM32MP15 176 if (bank == GPIO_BANK_Z) { 177 return true; 178 } 179 180 return false; 181 #endif 182 } 183 184 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 185 { 186 #if STM32MP13 187 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 188 #endif 189 #if STM32MP15 190 if (bank == GPIO_BANK_Z) { 191 return GPIOZ; 192 } 193 194 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 195 #endif 196 197 return GPIOA + (bank - GPIO_BANK_A); 198 } 199 200 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 201 { 202 const char *node_compatible = NULL; 203 204 switch (bank) { 205 case GPIO_BANK_A: 206 case GPIO_BANK_B: 207 case GPIO_BANK_C: 208 case GPIO_BANK_D: 209 case GPIO_BANK_E: 210 case GPIO_BANK_F: 211 case GPIO_BANK_G: 212 case GPIO_BANK_H: 213 case GPIO_BANK_I: 214 #if STM32MP13 215 node_compatible = "st,stm32mp135-pinctrl"; 216 break; 217 #endif 218 #if STM32MP15 219 case GPIO_BANK_J: 220 case GPIO_BANK_K: 221 node_compatible = "st,stm32mp157-pinctrl"; 222 break; 223 case GPIO_BANK_Z: 224 node_compatible = "st,stm32mp157-z-pinctrl"; 225 break; 226 #endif 227 default: 228 panic(); 229 } 230 231 return fdt_node_offset_by_compatible(fdt, -1, node_compatible); 232 } 233 234 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 235 /* 236 * UART Management 237 */ 238 static const uintptr_t stm32mp1_uart_addresses[8] = { 239 USART1_BASE, 240 USART2_BASE, 241 USART3_BASE, 242 UART4_BASE, 243 UART5_BASE, 244 USART6_BASE, 245 UART7_BASE, 246 UART8_BASE, 247 }; 248 249 uintptr_t get_uart_address(uint32_t instance_nb) 250 { 251 if ((instance_nb == 0U) || 252 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 253 return 0U; 254 } 255 256 return stm32mp1_uart_addresses[instance_nb - 1U]; 257 } 258 #endif 259 260 #if STM32MP_USB_PROGRAMMER 261 struct gpio_bank_pin_list { 262 uint32_t bank; 263 uint32_t pin; 264 }; 265 266 static const struct gpio_bank_pin_list gpio_list[] = { 267 { /* USART2_RX: GPIOA3 */ 268 .bank = 0U, 269 .pin = 3U, 270 }, 271 { /* USART3_RX: GPIOB12 */ 272 .bank = 1U, 273 .pin = 12U, 274 }, 275 { /* UART4_RX: GPIOB2 */ 276 .bank = 1U, 277 .pin = 2U, 278 }, 279 { /* UART5_RX: GPIOB4 */ 280 .bank = 1U, 281 .pin = 5U, 282 }, 283 { /* USART6_RX: GPIOC7 */ 284 .bank = 2U, 285 .pin = 7U, 286 }, 287 { /* UART7_RX: GPIOF6 */ 288 .bank = 5U, 289 .pin = 6U, 290 }, 291 { /* UART8_RX: GPIOE0 */ 292 .bank = 4U, 293 .pin = 0U, 294 }, 295 }; 296 297 void stm32mp1_deconfigure_uart_pins(void) 298 { 299 size_t i; 300 301 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 302 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 303 } 304 } 305 #endif 306 307 uint32_t stm32mp_get_chip_version(void) 308 { 309 #if STM32MP13 310 return stm32mp1_syscfg_get_chip_version(); 311 #endif 312 #if STM32MP15 313 uint32_t version = 0U; 314 315 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 316 INFO("Cannot get CPU version, debug disabled\n"); 317 return 0U; 318 } 319 320 return version; 321 #endif 322 } 323 324 uint32_t stm32mp_get_chip_dev_id(void) 325 { 326 #if STM32MP13 327 return stm32mp1_syscfg_get_chip_dev_id(); 328 #endif 329 #if STM32MP15 330 uint32_t dev_id; 331 332 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 333 INFO("Use default chip ID, debug disabled\n"); 334 dev_id = STM32MP1_CHIP_ID; 335 } 336 337 return dev_id; 338 #endif 339 } 340 341 static uint32_t get_part_number(void) 342 { 343 static uint32_t part_number; 344 345 if (part_number != 0U) { 346 return part_number; 347 } 348 349 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 350 panic(); 351 } 352 353 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 354 PART_NUMBER_OTP_PART_SHIFT; 355 356 part_number |= stm32mp_get_chip_dev_id() << 16; 357 358 return part_number; 359 } 360 361 #if STM32MP15 362 static uint32_t get_cpu_package(void) 363 { 364 uint32_t package; 365 366 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 367 panic(); 368 } 369 370 package = (package & PACKAGE_OTP_PKG_MASK) >> 371 PACKAGE_OTP_PKG_SHIFT; 372 373 return package; 374 } 375 #endif 376 377 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 378 { 379 char *cpu_s, *cpu_r, *pkg; 380 381 /* MPUs Part Numbers */ 382 switch (get_part_number()) { 383 #if STM32MP13 384 case STM32MP135F_PART_NB: 385 cpu_s = "135F"; 386 break; 387 case STM32MP135D_PART_NB: 388 cpu_s = "135D"; 389 break; 390 case STM32MP135C_PART_NB: 391 cpu_s = "135C"; 392 break; 393 case STM32MP135A_PART_NB: 394 cpu_s = "135A"; 395 break; 396 case STM32MP133F_PART_NB: 397 cpu_s = "133F"; 398 break; 399 case STM32MP133D_PART_NB: 400 cpu_s = "133D"; 401 break; 402 case STM32MP133C_PART_NB: 403 cpu_s = "133C"; 404 break; 405 case STM32MP133A_PART_NB: 406 cpu_s = "133A"; 407 break; 408 case STM32MP131F_PART_NB: 409 cpu_s = "131F"; 410 break; 411 case STM32MP131D_PART_NB: 412 cpu_s = "131D"; 413 break; 414 case STM32MP131C_PART_NB: 415 cpu_s = "131C"; 416 break; 417 case STM32MP131A_PART_NB: 418 cpu_s = "131A"; 419 break; 420 #endif 421 #if STM32MP15 422 case STM32MP157C_PART_NB: 423 cpu_s = "157C"; 424 break; 425 case STM32MP157A_PART_NB: 426 cpu_s = "157A"; 427 break; 428 case STM32MP153C_PART_NB: 429 cpu_s = "153C"; 430 break; 431 case STM32MP153A_PART_NB: 432 cpu_s = "153A"; 433 break; 434 case STM32MP151C_PART_NB: 435 cpu_s = "151C"; 436 break; 437 case STM32MP151A_PART_NB: 438 cpu_s = "151A"; 439 break; 440 case STM32MP157F_PART_NB: 441 cpu_s = "157F"; 442 break; 443 case STM32MP157D_PART_NB: 444 cpu_s = "157D"; 445 break; 446 case STM32MP153F_PART_NB: 447 cpu_s = "153F"; 448 break; 449 case STM32MP153D_PART_NB: 450 cpu_s = "153D"; 451 break; 452 case STM32MP151F_PART_NB: 453 cpu_s = "151F"; 454 break; 455 case STM32MP151D_PART_NB: 456 cpu_s = "151D"; 457 break; 458 #endif 459 default: 460 cpu_s = "????"; 461 break; 462 } 463 464 /* Package */ 465 #if STM32MP13 466 /* On STM32MP13, package is not present in OTP */ 467 pkg = ""; 468 #endif 469 #if STM32MP15 470 switch (get_cpu_package()) { 471 case PKG_AA_LFBGA448: 472 pkg = "AA"; 473 break; 474 case PKG_AB_LFBGA354: 475 pkg = "AB"; 476 break; 477 case PKG_AC_TFBGA361: 478 pkg = "AC"; 479 break; 480 case PKG_AD_TFBGA257: 481 pkg = "AD"; 482 break; 483 default: 484 pkg = "??"; 485 break; 486 } 487 #endif 488 489 /* REVISION */ 490 switch (stm32mp_get_chip_version()) { 491 case STM32MP1_REV_B: 492 cpu_r = "B"; 493 break; 494 case STM32MP1_REV_Z: 495 cpu_r = "Z"; 496 break; 497 default: 498 cpu_r = "?"; 499 break; 500 } 501 502 snprintf(name, STM32_SOC_NAME_SIZE, 503 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 504 } 505 506 void stm32mp_print_cpuinfo(void) 507 { 508 char name[STM32_SOC_NAME_SIZE]; 509 510 stm32mp_get_soc_name(name); 511 NOTICE("CPU: %s\n", name); 512 } 513 514 void stm32mp_print_boardinfo(void) 515 { 516 uint32_t board_id = 0; 517 518 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 519 return; 520 } 521 522 if (board_id != 0U) { 523 char rev[2]; 524 525 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 526 rev[1] = '\0'; 527 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 528 BOARD_ID2NB(board_id), 529 BOARD_ID2VARCPN(board_id), 530 BOARD_ID2VARFG(board_id), 531 rev, 532 BOARD_ID2BOM(board_id)); 533 } 534 } 535 536 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 537 bool stm32mp_is_single_core(void) 538 { 539 #if STM32MP13 540 return true; 541 #endif 542 #if STM32MP15 543 bool single_core = false; 544 545 switch (get_part_number()) { 546 case STM32MP151A_PART_NB: 547 case STM32MP151C_PART_NB: 548 case STM32MP151D_PART_NB: 549 case STM32MP151F_PART_NB: 550 single_core = true; 551 break; 552 default: 553 break; 554 } 555 556 return single_core; 557 #endif 558 } 559 560 /* Return true when device is in closed state */ 561 bool stm32mp_is_closed_device(void) 562 { 563 uint32_t value; 564 565 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 566 return true; 567 } 568 569 #if STM32MP13 570 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; 571 572 switch (value) { 573 case CFG0_OPEN_DEVICE: 574 return false; 575 case CFG0_CLOSED_DEVICE: 576 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: 577 case CFG0_CLOSED_DEVICE_NO_JTAG: 578 return true; 579 default: 580 panic(); 581 } 582 #endif 583 #if STM32MP15 584 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 585 #endif 586 } 587 588 /* Return true when device supports secure boot */ 589 bool stm32mp_is_auth_supported(void) 590 { 591 bool supported = false; 592 593 switch (get_part_number()) { 594 #if STM32MP13 595 case STM32MP131C_PART_NB: 596 case STM32MP131F_PART_NB: 597 case STM32MP133C_PART_NB: 598 case STM32MP133F_PART_NB: 599 case STM32MP135C_PART_NB: 600 case STM32MP135F_PART_NB: 601 #endif 602 #if STM32MP15 603 case STM32MP151C_PART_NB: 604 case STM32MP151F_PART_NB: 605 case STM32MP153C_PART_NB: 606 case STM32MP153F_PART_NB: 607 case STM32MP157C_PART_NB: 608 case STM32MP157F_PART_NB: 609 #endif 610 supported = true; 611 break; 612 default: 613 break; 614 } 615 616 return supported; 617 } 618 619 uint32_t stm32_iwdg_get_instance(uintptr_t base) 620 { 621 switch (base) { 622 case IWDG1_BASE: 623 return IWDG1_INST; 624 case IWDG2_BASE: 625 return IWDG2_INST; 626 default: 627 panic(); 628 } 629 } 630 631 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 632 { 633 uint32_t iwdg_cfg = 0U; 634 uint32_t otp_value; 635 636 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 637 panic(); 638 } 639 640 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 641 iwdg_cfg |= IWDG_HW_ENABLED; 642 } 643 644 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 645 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 646 } 647 648 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 649 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 650 } 651 652 return iwdg_cfg; 653 } 654 655 #if defined(IMAGE_BL2) 656 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 657 { 658 uint32_t otp_value; 659 uint32_t otp; 660 uint32_t result; 661 662 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 663 panic(); 664 } 665 666 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 667 panic(); 668 } 669 670 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 671 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 672 } 673 674 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 675 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 676 } 677 678 result = bsec_write_otp(otp_value, otp); 679 if (result != BSEC_OK) { 680 return result; 681 } 682 683 /* Sticky lock OTP_IWDG (read and write) */ 684 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 685 (bsec_set_sw_lock(otp) != BSEC_OK)) { 686 return BSEC_LOCK_FAIL; 687 } 688 689 return BSEC_OK; 690 } 691 #endif 692 693 #if STM32MP_USE_STM32IMAGE 694 /* Get the non-secure DDR size */ 695 uint32_t stm32mp_get_ddr_ns_size(void) 696 { 697 static uint32_t ddr_ns_size; 698 uint32_t ddr_size; 699 700 if (ddr_ns_size != 0U) { 701 return ddr_ns_size; 702 } 703 704 ddr_size = dt_get_ddr_size(); 705 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 706 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 707 panic(); 708 } 709 710 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 711 712 return ddr_ns_size; 713 } 714 #endif /* STM32MP_USE_STM32IMAGE */ 715 716 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 717 { 718 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 719 720 clk_enable(RTCAPB); 721 722 mmio_clrsetbits_32(bkpr_itf_idx, 723 TAMP_BOOT_MODE_ITF_MASK, 724 ((interface << 4) | (instance & 0xFU)) << 725 TAMP_BOOT_MODE_ITF_SHIFT); 726 727 clk_disable(RTCAPB); 728 } 729 730 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 731 { 732 static uint32_t itf; 733 734 if (itf == 0U) { 735 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 736 737 clk_enable(RTCAPB); 738 739 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 740 TAMP_BOOT_MODE_ITF_SHIFT; 741 742 clk_disable(RTCAPB); 743 } 744 745 *interface = itf >> 4; 746 *instance = itf & 0xFU; 747 } 748 749 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 750 void stm32mp1_fwu_set_boot_idx(void) 751 { 752 clk_enable(RTCAPB); 753 mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID), 754 TAMP_BOOT_FWU_INFO_IDX_MSK, 755 (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) & 756 TAMP_BOOT_FWU_INFO_IDX_MSK); 757 clk_disable(RTCAPB); 758 } 759 760 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void) 761 { 762 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 763 uint32_t try_cnt; 764 765 clk_enable(RTCAPB); 766 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >> 767 TAMP_BOOT_FWU_INFO_CNT_OFF; 768 769 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT); 770 771 if (try_cnt != 0U) { 772 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 773 (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF); 774 } 775 clk_disable(RTCAPB); 776 777 return try_cnt; 778 } 779 780 void stm32_set_max_fwu_trial_boot_cnt(void) 781 { 782 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 783 784 clk_enable(RTCAPB); 785 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 786 (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) & 787 TAMP_BOOT_FWU_INFO_CNT_MSK); 788 clk_disable(RTCAPB); 789 } 790 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 791