1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #if STM32MP13 41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 42 #endif 43 #if STM32MP15 44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 45 #endif 46 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 47 #define TAMP_BOOT_MODE_ITF_SHIFT 8 48 49 /* 50 * Backup register to store fwu update information. 51 * It should be writeable only by secure world, but also readable by non secure 52 * (so it should be in Zone 2). 53 */ 54 #define TAMP_BOOT_FWU_INFO_REG_ID U(10) 55 #define TAMP_BOOT_FWU_INFO_IDX_MSK U(0xF) 56 #define TAMP_BOOT_FWU_INFO_IDX_OFF U(0) 57 #define TAMP_BOOT_FWU_INFO_CNT_MSK U(0xF0) 58 #define TAMP_BOOT_FWU_INFO_CNT_OFF U(4) 59 60 #if defined(IMAGE_BL2) 61 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 62 STM32MP_SYSRAM_SIZE, \ 63 MT_MEMORY | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 #elif defined(IMAGE_BL32) 68 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 69 STM32MP_SEC_SYSRAM_SIZE, \ 70 MT_MEMORY | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 76 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 77 STM32MP_NS_SYSRAM_SIZE, \ 78 MT_DEVICE | \ 79 MT_RW | \ 80 MT_NS | \ 81 MT_EXECUTE_NEVER) 82 #endif 83 84 #if STM32MP13 85 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 86 SRAMS_SIZE_2MB_ALIGNED, \ 87 MT_MEMORY | \ 88 MT_RW | \ 89 MT_SECURE | \ 90 MT_EXECUTE_NEVER) 91 #endif 92 93 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 94 STM32MP1_DEVICE1_SIZE, \ 95 MT_DEVICE | \ 96 MT_RW | \ 97 MT_SECURE | \ 98 MT_EXECUTE_NEVER) 99 100 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 101 STM32MP1_DEVICE2_SIZE, \ 102 MT_DEVICE | \ 103 MT_RW | \ 104 MT_SECURE | \ 105 MT_EXECUTE_NEVER) 106 107 #if defined(IMAGE_BL2) 108 static const mmap_region_t stm32mp1_mmap[] = { 109 MAP_SEC_SYSRAM, 110 #if STM32MP13 111 MAP_SRAM_ALL, 112 #endif 113 MAP_DEVICE1, 114 #if STM32MP_RAW_NAND 115 MAP_DEVICE2, 116 #endif 117 {0} 118 }; 119 #endif 120 #if defined(IMAGE_BL32) 121 static const mmap_region_t stm32mp1_mmap[] = { 122 MAP_SEC_SYSRAM, 123 MAP_NS_SYSRAM, 124 MAP_DEVICE1, 125 MAP_DEVICE2, 126 {0} 127 }; 128 #endif 129 130 void configure_mmu(void) 131 { 132 mmap_add(stm32mp1_mmap); 133 init_xlat_tables(); 134 135 enable_mmu_svc_mon(0); 136 } 137 138 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 139 { 140 #if STM32MP13 141 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 142 #endif 143 #if STM32MP15 144 if (bank == GPIO_BANK_Z) { 145 return GPIOZ_BASE; 146 } 147 148 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 149 #endif 150 151 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 152 } 153 154 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 155 { 156 #if STM32MP13 157 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 158 #endif 159 #if STM32MP15 160 if (bank == GPIO_BANK_Z) { 161 return 0; 162 } 163 164 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 165 #endif 166 167 return bank * GPIO_BANK_OFFSET; 168 } 169 170 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 171 { 172 #if STM32MP13 173 return true; 174 #endif 175 #if STM32MP15 176 if (bank == GPIO_BANK_Z) { 177 return true; 178 } 179 180 return false; 181 #endif 182 } 183 184 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 185 { 186 #if STM32MP13 187 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 188 #endif 189 #if STM32MP15 190 if (bank == GPIO_BANK_Z) { 191 return GPIOZ; 192 } 193 194 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 195 #endif 196 197 return GPIOA + (bank - GPIO_BANK_A); 198 } 199 200 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 201 { 202 switch (bank) { 203 case GPIO_BANK_A: 204 case GPIO_BANK_B: 205 case GPIO_BANK_C: 206 case GPIO_BANK_D: 207 case GPIO_BANK_E: 208 case GPIO_BANK_F: 209 case GPIO_BANK_G: 210 case GPIO_BANK_H: 211 case GPIO_BANK_I: 212 #if STM32MP15 213 case GPIO_BANK_J: 214 case GPIO_BANK_K: 215 #endif 216 return fdt_path_offset(fdt, "/soc/pin-controller"); 217 #if STM32MP15 218 case GPIO_BANK_Z: 219 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 220 #endif 221 default: 222 panic(); 223 } 224 } 225 226 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 227 /* 228 * UART Management 229 */ 230 static const uintptr_t stm32mp1_uart_addresses[8] = { 231 USART1_BASE, 232 USART2_BASE, 233 USART3_BASE, 234 UART4_BASE, 235 UART5_BASE, 236 USART6_BASE, 237 UART7_BASE, 238 UART8_BASE, 239 }; 240 241 uintptr_t get_uart_address(uint32_t instance_nb) 242 { 243 if ((instance_nb == 0U) || 244 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 245 return 0U; 246 } 247 248 return stm32mp1_uart_addresses[instance_nb - 1U]; 249 } 250 #endif 251 252 #if STM32MP_USB_PROGRAMMER 253 struct gpio_bank_pin_list { 254 uint32_t bank; 255 uint32_t pin; 256 }; 257 258 static const struct gpio_bank_pin_list gpio_list[] = { 259 { /* USART2_RX: GPIOA3 */ 260 .bank = 0U, 261 .pin = 3U, 262 }, 263 { /* USART3_RX: GPIOB12 */ 264 .bank = 1U, 265 .pin = 12U, 266 }, 267 { /* UART4_RX: GPIOB2 */ 268 .bank = 1U, 269 .pin = 2U, 270 }, 271 { /* UART5_RX: GPIOB4 */ 272 .bank = 1U, 273 .pin = 5U, 274 }, 275 { /* USART6_RX: GPIOC7 */ 276 .bank = 2U, 277 .pin = 7U, 278 }, 279 { /* UART7_RX: GPIOF6 */ 280 .bank = 5U, 281 .pin = 6U, 282 }, 283 { /* UART8_RX: GPIOE0 */ 284 .bank = 4U, 285 .pin = 0U, 286 }, 287 }; 288 289 void stm32mp1_deconfigure_uart_pins(void) 290 { 291 size_t i; 292 293 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 294 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 295 } 296 } 297 #endif 298 299 uint32_t stm32mp_get_chip_version(void) 300 { 301 #if STM32MP13 302 return stm32mp1_syscfg_get_chip_version(); 303 #endif 304 #if STM32MP15 305 uint32_t version = 0U; 306 307 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 308 INFO("Cannot get CPU version, debug disabled\n"); 309 return 0U; 310 } 311 312 return version; 313 #endif 314 } 315 316 uint32_t stm32mp_get_chip_dev_id(void) 317 { 318 #if STM32MP13 319 return stm32mp1_syscfg_get_chip_dev_id(); 320 #endif 321 #if STM32MP15 322 uint32_t dev_id; 323 324 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 325 INFO("Use default chip ID, debug disabled\n"); 326 dev_id = STM32MP1_CHIP_ID; 327 } 328 329 return dev_id; 330 #endif 331 } 332 333 static uint32_t get_part_number(void) 334 { 335 static uint32_t part_number; 336 337 if (part_number != 0U) { 338 return part_number; 339 } 340 341 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 342 panic(); 343 } 344 345 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 346 PART_NUMBER_OTP_PART_SHIFT; 347 348 part_number |= stm32mp_get_chip_dev_id() << 16; 349 350 return part_number; 351 } 352 353 #if STM32MP15 354 static uint32_t get_cpu_package(void) 355 { 356 uint32_t package; 357 358 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 359 panic(); 360 } 361 362 package = (package & PACKAGE_OTP_PKG_MASK) >> 363 PACKAGE_OTP_PKG_SHIFT; 364 365 return package; 366 } 367 #endif 368 369 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 370 { 371 char *cpu_s, *cpu_r, *pkg; 372 373 /* MPUs Part Numbers */ 374 switch (get_part_number()) { 375 #if STM32MP13 376 case STM32MP135F_PART_NB: 377 cpu_s = "135F"; 378 break; 379 case STM32MP135D_PART_NB: 380 cpu_s = "135D"; 381 break; 382 case STM32MP135C_PART_NB: 383 cpu_s = "135C"; 384 break; 385 case STM32MP135A_PART_NB: 386 cpu_s = "135A"; 387 break; 388 case STM32MP133F_PART_NB: 389 cpu_s = "133F"; 390 break; 391 case STM32MP133D_PART_NB: 392 cpu_s = "133D"; 393 break; 394 case STM32MP133C_PART_NB: 395 cpu_s = "133C"; 396 break; 397 case STM32MP133A_PART_NB: 398 cpu_s = "133A"; 399 break; 400 case STM32MP131F_PART_NB: 401 cpu_s = "131F"; 402 break; 403 case STM32MP131D_PART_NB: 404 cpu_s = "131D"; 405 break; 406 case STM32MP131C_PART_NB: 407 cpu_s = "131C"; 408 break; 409 case STM32MP131A_PART_NB: 410 cpu_s = "131A"; 411 break; 412 #endif 413 #if STM32MP15 414 case STM32MP157C_PART_NB: 415 cpu_s = "157C"; 416 break; 417 case STM32MP157A_PART_NB: 418 cpu_s = "157A"; 419 break; 420 case STM32MP153C_PART_NB: 421 cpu_s = "153C"; 422 break; 423 case STM32MP153A_PART_NB: 424 cpu_s = "153A"; 425 break; 426 case STM32MP151C_PART_NB: 427 cpu_s = "151C"; 428 break; 429 case STM32MP151A_PART_NB: 430 cpu_s = "151A"; 431 break; 432 case STM32MP157F_PART_NB: 433 cpu_s = "157F"; 434 break; 435 case STM32MP157D_PART_NB: 436 cpu_s = "157D"; 437 break; 438 case STM32MP153F_PART_NB: 439 cpu_s = "153F"; 440 break; 441 case STM32MP153D_PART_NB: 442 cpu_s = "153D"; 443 break; 444 case STM32MP151F_PART_NB: 445 cpu_s = "151F"; 446 break; 447 case STM32MP151D_PART_NB: 448 cpu_s = "151D"; 449 break; 450 #endif 451 default: 452 cpu_s = "????"; 453 break; 454 } 455 456 /* Package */ 457 #if STM32MP13 458 /* On STM32MP13, package is not present in OTP */ 459 pkg = ""; 460 #endif 461 #if STM32MP15 462 switch (get_cpu_package()) { 463 case PKG_AA_LFBGA448: 464 pkg = "AA"; 465 break; 466 case PKG_AB_LFBGA354: 467 pkg = "AB"; 468 break; 469 case PKG_AC_TFBGA361: 470 pkg = "AC"; 471 break; 472 case PKG_AD_TFBGA257: 473 pkg = "AD"; 474 break; 475 default: 476 pkg = "??"; 477 break; 478 } 479 #endif 480 481 /* REVISION */ 482 switch (stm32mp_get_chip_version()) { 483 case STM32MP1_REV_B: 484 cpu_r = "B"; 485 break; 486 case STM32MP1_REV_Z: 487 cpu_r = "Z"; 488 break; 489 default: 490 cpu_r = "?"; 491 break; 492 } 493 494 snprintf(name, STM32_SOC_NAME_SIZE, 495 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 496 } 497 498 void stm32mp_print_cpuinfo(void) 499 { 500 char name[STM32_SOC_NAME_SIZE]; 501 502 stm32mp_get_soc_name(name); 503 NOTICE("CPU: %s\n", name); 504 } 505 506 void stm32mp_print_boardinfo(void) 507 { 508 uint32_t board_id = 0; 509 510 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 511 return; 512 } 513 514 if (board_id != 0U) { 515 char rev[2]; 516 517 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 518 rev[1] = '\0'; 519 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 520 BOARD_ID2NB(board_id), 521 BOARD_ID2VARCPN(board_id), 522 BOARD_ID2VARFG(board_id), 523 rev, 524 BOARD_ID2BOM(board_id)); 525 } 526 } 527 528 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 529 bool stm32mp_is_single_core(void) 530 { 531 #if STM32MP13 532 return true; 533 #endif 534 #if STM32MP15 535 bool single_core = false; 536 537 switch (get_part_number()) { 538 case STM32MP151A_PART_NB: 539 case STM32MP151C_PART_NB: 540 case STM32MP151D_PART_NB: 541 case STM32MP151F_PART_NB: 542 single_core = true; 543 break; 544 default: 545 break; 546 } 547 548 return single_core; 549 #endif 550 } 551 552 /* Return true when device is in closed state */ 553 bool stm32mp_is_closed_device(void) 554 { 555 uint32_t value; 556 557 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 558 return true; 559 } 560 561 #if STM32MP13 562 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; 563 564 switch (value) { 565 case CFG0_OPEN_DEVICE: 566 return false; 567 case CFG0_CLOSED_DEVICE: 568 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: 569 case CFG0_CLOSED_DEVICE_NO_JTAG: 570 return true; 571 default: 572 panic(); 573 } 574 #endif 575 #if STM32MP15 576 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 577 #endif 578 } 579 580 /* Return true when device supports secure boot */ 581 bool stm32mp_is_auth_supported(void) 582 { 583 bool supported = false; 584 585 switch (get_part_number()) { 586 #if STM32MP13 587 case STM32MP131C_PART_NB: 588 case STM32MP131F_PART_NB: 589 case STM32MP133C_PART_NB: 590 case STM32MP133F_PART_NB: 591 case STM32MP135C_PART_NB: 592 case STM32MP135F_PART_NB: 593 #endif 594 #if STM32MP15 595 case STM32MP151C_PART_NB: 596 case STM32MP151F_PART_NB: 597 case STM32MP153C_PART_NB: 598 case STM32MP153F_PART_NB: 599 case STM32MP157C_PART_NB: 600 case STM32MP157F_PART_NB: 601 #endif 602 supported = true; 603 break; 604 default: 605 break; 606 } 607 608 return supported; 609 } 610 611 uint32_t stm32_iwdg_get_instance(uintptr_t base) 612 { 613 switch (base) { 614 case IWDG1_BASE: 615 return IWDG1_INST; 616 case IWDG2_BASE: 617 return IWDG2_INST; 618 default: 619 panic(); 620 } 621 } 622 623 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 624 { 625 uint32_t iwdg_cfg = 0U; 626 uint32_t otp_value; 627 628 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 629 panic(); 630 } 631 632 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 633 iwdg_cfg |= IWDG_HW_ENABLED; 634 } 635 636 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 637 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 638 } 639 640 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 641 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 642 } 643 644 return iwdg_cfg; 645 } 646 647 #if defined(IMAGE_BL2) 648 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 649 { 650 uint32_t otp_value; 651 uint32_t otp; 652 uint32_t result; 653 654 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 655 panic(); 656 } 657 658 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 659 panic(); 660 } 661 662 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 663 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 664 } 665 666 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 667 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 668 } 669 670 result = bsec_write_otp(otp_value, otp); 671 if (result != BSEC_OK) { 672 return result; 673 } 674 675 /* Sticky lock OTP_IWDG (read and write) */ 676 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 677 (bsec_set_sw_lock(otp) != BSEC_OK)) { 678 return BSEC_LOCK_FAIL; 679 } 680 681 return BSEC_OK; 682 } 683 #endif 684 685 #if STM32MP_USE_STM32IMAGE 686 /* Get the non-secure DDR size */ 687 uint32_t stm32mp_get_ddr_ns_size(void) 688 { 689 static uint32_t ddr_ns_size; 690 uint32_t ddr_size; 691 692 if (ddr_ns_size != 0U) { 693 return ddr_ns_size; 694 } 695 696 ddr_size = dt_get_ddr_size(); 697 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 698 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 699 panic(); 700 } 701 702 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 703 704 return ddr_ns_size; 705 } 706 #endif /* STM32MP_USE_STM32IMAGE */ 707 708 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 709 { 710 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 711 712 clk_enable(RTCAPB); 713 714 mmio_clrsetbits_32(bkpr_itf_idx, 715 TAMP_BOOT_MODE_ITF_MASK, 716 ((interface << 4) | (instance & 0xFU)) << 717 TAMP_BOOT_MODE_ITF_SHIFT); 718 719 clk_disable(RTCAPB); 720 } 721 722 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 723 { 724 static uint32_t itf; 725 726 if (itf == 0U) { 727 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 728 729 clk_enable(RTCAPB); 730 731 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 732 TAMP_BOOT_MODE_ITF_SHIFT; 733 734 clk_disable(RTCAPB); 735 } 736 737 *interface = itf >> 4; 738 *instance = itf & 0xFU; 739 } 740 741 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 742 void stm32mp1_fwu_set_boot_idx(void) 743 { 744 clk_enable(RTCAPB); 745 mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID), 746 TAMP_BOOT_FWU_INFO_IDX_MSK, 747 (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) & 748 TAMP_BOOT_FWU_INFO_IDX_MSK); 749 clk_disable(RTCAPB); 750 } 751 752 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void) 753 { 754 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 755 uint32_t try_cnt; 756 757 clk_enable(RTCAPB); 758 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >> 759 TAMP_BOOT_FWU_INFO_CNT_OFF; 760 761 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT); 762 763 if (try_cnt != 0U) { 764 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 765 (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF); 766 } 767 clk_disable(RTCAPB); 768 769 return try_cnt; 770 } 771 772 void stm32_set_max_fwu_trial_boot_cnt(void) 773 { 774 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 775 776 clk_enable(RTCAPB); 777 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 778 (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) & 779 TAMP_BOOT_FWU_INFO_CNT_MSK); 780 clk_disable(RTCAPB); 781 } 782 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 783