1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <drivers/st/stm32_iwdg.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARIANT_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARIANT_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 24 25 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 26 BOARD_ID_BOARD_NB_SHIFT) 27 #define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \ 28 BOARD_ID_VARIANT_SHIFT) 29 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 30 BOARD_ID_REVISION_SHIFT) 31 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 32 33 #if defined(IMAGE_BL2) 34 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 35 STM32MP_SYSRAM_SIZE, \ 36 MT_MEMORY | \ 37 MT_RW | \ 38 MT_SECURE | \ 39 MT_EXECUTE_NEVER) 40 #elif defined(IMAGE_BL32) 41 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 42 STM32MP_SEC_SYSRAM_SIZE, \ 43 MT_MEMORY | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 49 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 50 STM32MP_NS_SYSRAM_SIZE, \ 51 MT_DEVICE | \ 52 MT_RW | \ 53 MT_NS | \ 54 MT_EXECUTE_NEVER) 55 #endif 56 57 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 58 STM32MP1_DEVICE1_SIZE, \ 59 MT_DEVICE | \ 60 MT_RW | \ 61 MT_SECURE | \ 62 MT_EXECUTE_NEVER) 63 64 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 65 STM32MP1_DEVICE2_SIZE, \ 66 MT_DEVICE | \ 67 MT_RW | \ 68 MT_SECURE | \ 69 MT_EXECUTE_NEVER) 70 71 #if defined(IMAGE_BL2) 72 static const mmap_region_t stm32mp1_mmap[] = { 73 MAP_SEC_SYSRAM, 74 MAP_DEVICE1, 75 MAP_DEVICE2, 76 {0} 77 }; 78 #endif 79 #if defined(IMAGE_BL32) 80 static const mmap_region_t stm32mp1_mmap[] = { 81 MAP_SEC_SYSRAM, 82 MAP_NS_SYSRAM, 83 MAP_DEVICE1, 84 MAP_DEVICE2, 85 {0} 86 }; 87 #endif 88 89 void configure_mmu(void) 90 { 91 mmap_add(stm32mp1_mmap); 92 init_xlat_tables(); 93 94 enable_mmu_svc_mon(0); 95 } 96 97 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 98 { 99 if (bank == GPIO_BANK_Z) { 100 return GPIOZ_BASE; 101 } 102 103 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 104 105 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 106 } 107 108 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 109 { 110 if (bank == GPIO_BANK_Z) { 111 return 0; 112 } 113 114 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 115 116 return bank * GPIO_BANK_OFFSET; 117 } 118 119 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 120 { 121 if (bank == GPIO_BANK_Z) { 122 return GPIOZ; 123 } 124 125 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 126 127 return GPIOA + (bank - GPIO_BANK_A); 128 } 129 130 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 131 { 132 switch (bank) { 133 case GPIO_BANK_A: 134 case GPIO_BANK_B: 135 case GPIO_BANK_C: 136 case GPIO_BANK_D: 137 case GPIO_BANK_E: 138 case GPIO_BANK_F: 139 case GPIO_BANK_G: 140 case GPIO_BANK_H: 141 case GPIO_BANK_I: 142 case GPIO_BANK_J: 143 case GPIO_BANK_K: 144 return fdt_path_offset(fdt, "/soc/pin-controller"); 145 case GPIO_BANK_Z: 146 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 147 default: 148 panic(); 149 } 150 } 151 152 static int get_part_number(uint32_t *part_nb) 153 { 154 uint32_t part_number; 155 uint32_t dev_id; 156 157 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 158 return -1; 159 } 160 161 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 162 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 163 return -1; 164 } 165 166 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 167 PART_NUMBER_OTP_PART_SHIFT; 168 169 *part_nb = part_number | (dev_id << 16); 170 171 return 0; 172 } 173 174 static int get_cpu_package(uint32_t *cpu_package) 175 { 176 uint32_t package; 177 178 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 179 ERROR("BSEC: PACKAGE_OTP Error\n"); 180 return -1; 181 } 182 183 *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> 184 PACKAGE_OTP_PKG_SHIFT; 185 186 return 0; 187 } 188 189 void stm32mp_print_cpuinfo(void) 190 { 191 const char *cpu_s, *cpu_r, *pkg; 192 uint32_t part_number; 193 uint32_t cpu_package; 194 uint32_t chip_dev_id; 195 int ret; 196 197 /* MPUs Part Numbers */ 198 ret = get_part_number(&part_number); 199 if (ret < 0) { 200 WARN("Cannot get part number\n"); 201 return; 202 } 203 204 switch (part_number) { 205 case STM32MP157C_PART_NB: 206 cpu_s = "157C"; 207 break; 208 case STM32MP157A_PART_NB: 209 cpu_s = "157A"; 210 break; 211 case STM32MP153C_PART_NB: 212 cpu_s = "153C"; 213 break; 214 case STM32MP153A_PART_NB: 215 cpu_s = "153A"; 216 break; 217 case STM32MP151C_PART_NB: 218 cpu_s = "151C"; 219 break; 220 case STM32MP151A_PART_NB: 221 cpu_s = "151A"; 222 break; 223 default: 224 cpu_s = "????"; 225 break; 226 } 227 228 /* Package */ 229 ret = get_cpu_package(&cpu_package); 230 if (ret < 0) { 231 WARN("Cannot get CPU package\n"); 232 return; 233 } 234 235 switch (cpu_package) { 236 case PKG_AA_LFBGA448: 237 pkg = "AA"; 238 break; 239 case PKG_AB_LFBGA354: 240 pkg = "AB"; 241 break; 242 case PKG_AC_TFBGA361: 243 pkg = "AC"; 244 break; 245 case PKG_AD_TFBGA257: 246 pkg = "AD"; 247 break; 248 default: 249 pkg = "??"; 250 break; 251 } 252 253 /* REVISION */ 254 ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); 255 if (ret < 0) { 256 WARN("Cannot get CPU version\n"); 257 return; 258 } 259 260 switch (chip_dev_id) { 261 case STM32MP1_REV_B: 262 cpu_r = "B"; 263 break; 264 default: 265 cpu_r = "?"; 266 break; 267 } 268 269 NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); 270 } 271 272 void stm32mp_print_boardinfo(void) 273 { 274 uint32_t board_id; 275 uint32_t board_otp; 276 int bsec_node, bsec_board_id_node; 277 void *fdt; 278 const fdt32_t *cuint; 279 280 if (fdt_get_address(&fdt) == 0) { 281 panic(); 282 } 283 284 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 285 if (bsec_node < 0) { 286 return; 287 } 288 289 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 290 if (bsec_board_id_node <= 0) { 291 return; 292 } 293 294 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 295 if (cuint == NULL) { 296 panic(); 297 } 298 299 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 300 301 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 302 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 303 return; 304 } 305 306 if (board_id != 0U) { 307 char rev[2]; 308 309 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 310 rev[1] = '\0'; 311 NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n", 312 BOARD_ID2NB(board_id), 313 BOARD_ID2VAR(board_id), 314 rev, 315 BOARD_ID2BOM(board_id)); 316 } 317 } 318 319 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 320 bool stm32mp_is_single_core(void) 321 { 322 uint32_t part_number; 323 bool ret = false; 324 325 if (get_part_number(&part_number) < 0) { 326 ERROR("Invalid part number, assume single core chip"); 327 return true; 328 } 329 330 switch (part_number) { 331 case STM32MP151A_PART_NB: 332 case STM32MP151C_PART_NB: 333 ret = true; 334 break; 335 336 default: 337 break; 338 } 339 340 return ret; 341 } 342 343 /* Return true when device is in closed state */ 344 bool stm32mp_is_closed_device(void) 345 { 346 uint32_t value; 347 348 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 349 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 350 return true; 351 } 352 353 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 354 } 355 356 uint32_t stm32_iwdg_get_instance(uintptr_t base) 357 { 358 switch (base) { 359 case IWDG1_BASE: 360 return IWDG1_INST; 361 case IWDG2_BASE: 362 return IWDG2_INST; 363 default: 364 panic(); 365 } 366 } 367 368 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 369 { 370 uint32_t iwdg_cfg = 0U; 371 uint32_t otp_value; 372 373 #if defined(IMAGE_BL2) 374 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 375 panic(); 376 } 377 #endif 378 379 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 380 panic(); 381 } 382 383 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 384 iwdg_cfg |= IWDG_HW_ENABLED; 385 } 386 387 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 388 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 389 } 390 391 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 392 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 393 } 394 395 return iwdg_cfg; 396 } 397 398 #if defined(IMAGE_BL2) 399 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 400 { 401 uint32_t otp; 402 uint32_t result; 403 404 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 405 panic(); 406 } 407 408 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 409 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 410 } 411 412 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 413 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 414 } 415 416 result = bsec_write_otp(otp, HW2_OTP); 417 if (result != BSEC_OK) { 418 return result; 419 } 420 421 /* Sticky lock OTP_IWDG (read and write) */ 422 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 423 !bsec_write_sw_lock(HW2_OTP, 1U)) { 424 return BSEC_LOCK_FAIL; 425 } 426 427 return BSEC_OK; 428 } 429 #endif 430 431 /* Get the non-secure DDR size */ 432 uint32_t stm32mp_get_ddr_ns_size(void) 433 { 434 static uint32_t ddr_ns_size; 435 uint32_t ddr_size; 436 437 if (ddr_ns_size != 0U) { 438 return ddr_ns_size; 439 } 440 441 ddr_size = dt_get_ddr_size(); 442 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 443 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 444 panic(); 445 } 446 447 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 448 449 return ddr_ns_size; 450 } 451