1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/st/stm32mp1_clk.h> 17 #include <drivers/st/stm32mp1_rcc.h> 18 #include <dt-bindings/clock/stm32mp1-clks.h> 19 #include <lib/mmio.h> 20 #include <lib/psci/psci.h> 21 #include <plat/common/platform.h> 22 23 #include <boot_api.h> 24 #include <stm32mp1_private.h> 25 26 static uint32_t stm32_sec_entrypoint; 27 static uint32_t cntfrq_core0; 28 29 #define SEND_SECURE_IT_TO_CORE_1 0x20000U 30 31 /******************************************************************************* 32 * STM32MP1 handler called when a CPU is about to enter standby. 33 * call by core 1 to enter in wfi 34 ******************************************************************************/ 35 static void stm32_cpu_standby(plat_local_state_t cpu_state) 36 { 37 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; 38 39 assert(cpu_state == ARM_LOCAL_STATE_RET); 40 41 /* 42 * Enter standby state 43 * dsb is good practice before using wfi to enter low power states 44 */ 45 dsb(); 46 while (interrupt == GIC_SPURIOUS_INTERRUPT) { 47 wfi(); 48 49 /* Acknoledge IT */ 50 interrupt = gicv2_acknowledge_interrupt(); 51 /* If Interrupt == 1022 it will be acknowledged by non secure */ 52 if ((interrupt != PENDING_G1_INTID) && 53 (interrupt != GIC_SPURIOUS_INTERRUPT)) { 54 gicv2_end_of_interrupt(interrupt); 55 } 56 } 57 } 58 59 /******************************************************************************* 60 * STM32MP1 handler called when a power domain is about to be turned on. The 61 * mpidr determines the CPU to be turned on. 62 * call by core 0 to activate core 1 63 ******************************************************************************/ 64 static int stm32_pwr_domain_on(u_register_t mpidr) 65 { 66 unsigned long current_cpu_mpidr = read_mpidr_el1(); 67 uint32_t tamp_clk_off = 0; 68 uint32_t bkpr_core1_addr = 69 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); 70 uint32_t bkpr_core1_magic = 71 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); 72 73 if (mpidr == current_cpu_mpidr) { 74 return PSCI_E_INVALID_PARAMS; 75 } 76 77 if ((stm32_sec_entrypoint < STM32MP1_SRAM_BASE) || 78 (stm32_sec_entrypoint > (STM32MP1_SRAM_BASE + 79 (STM32MP1_SRAM_SIZE - 1)))) { 80 return PSCI_E_INVALID_ADDRESS; 81 } 82 83 if (!stm32mp1_clk_is_enabled(RTCAPB)) { 84 tamp_clk_off = 1; 85 if (stm32mp1_clk_enable(RTCAPB) != 0) { 86 panic(); 87 } 88 } 89 90 cntfrq_core0 = read_cntfrq_el0(); 91 92 /* Write entrypoint in backup RAM register */ 93 mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint); 94 95 /* Write magic number in backup register */ 96 mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER); 97 98 if (tamp_clk_off != 0U) { 99 if (stm32mp1_clk_disable(RTCAPB) != 0) { 100 panic(); 101 } 102 } 103 104 /* Generate an IT to core 1 */ 105 mmio_write_32(STM32MP1_GICD_BASE + GICD_SGIR, 106 SEND_SECURE_IT_TO_CORE_1 | ARM_IRQ_SEC_SGI_0); 107 108 return PSCI_E_SUCCESS; 109 } 110 111 /******************************************************************************* 112 * STM32MP1 handler called when a power domain is about to be turned off. The 113 * target_state encodes the power state that each level should transition to. 114 ******************************************************************************/ 115 static void stm32_pwr_domain_off(const psci_power_state_t *target_state) 116 { 117 /* Nothing to do */ 118 } 119 120 /******************************************************************************* 121 * STM32MP1 handler called when a power domain is about to be suspended. The 122 * target_state encodes the power state that each level should transition to. 123 ******************************************************************************/ 124 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) 125 { 126 /* Nothing to do, power domain is not disabled */ 127 } 128 129 /******************************************************************************* 130 * STM32MP1 handler called when a power domain has just been powered on after 131 * being turned off earlier. The target_state encodes the low power state that 132 * each level has woken up from. 133 * call by core 1 just after wake up 134 ******************************************************************************/ 135 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) 136 { 137 stm32mp1_gic_pcpu_init(); 138 139 write_cntfrq_el0(cntfrq_core0); 140 } 141 142 /******************************************************************************* 143 * STM32MP1 handler called when a power domain has just been powered on after 144 * having been suspended earlier. The target_state encodes the low power state 145 * that each level has woken up from. 146 ******************************************************************************/ 147 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t 148 *target_state) 149 { 150 /* Nothing to do, power domain is not disabled */ 151 } 152 153 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t 154 *target_state) 155 { 156 ERROR("stm32mpu1 Power Down WFI: operation not handled.\n"); 157 panic(); 158 } 159 160 static void __dead2 stm32_system_off(void) 161 { 162 ERROR("stm32mpu1 System Off: operation not handled.\n"); 163 panic(); 164 } 165 166 static void __dead2 stm32_system_reset(void) 167 { 168 mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST); 169 170 /* Loop in case system reset is not immediately caught */ 171 for ( ; ; ) { 172 ; 173 } 174 } 175 176 static int stm32_validate_power_state(unsigned int power_state, 177 psci_power_state_t *req_state) 178 { 179 int pstate = psci_get_pstate_type(power_state); 180 181 if (pstate != 0) { 182 return PSCI_E_INVALID_PARAMS; 183 } 184 185 if (psci_get_pstate_pwrlvl(power_state)) { 186 return PSCI_E_INVALID_PARAMS; 187 } 188 189 if (psci_get_pstate_id(power_state)) { 190 return PSCI_E_INVALID_PARAMS; 191 } 192 193 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET; 194 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN; 195 196 return PSCI_E_SUCCESS; 197 } 198 199 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint) 200 { 201 /* The non-secure entry point must be in DDR */ 202 if (entrypoint < STM32MP1_DDR_BASE) { 203 return PSCI_E_INVALID_ADDRESS; 204 } 205 206 return PSCI_E_SUCCESS; 207 } 208 209 static int stm32_node_hw_state(u_register_t target_cpu, 210 unsigned int power_level) 211 { 212 /* 213 * The format of 'power_level' is implementation-defined, but 0 must 214 * mean a CPU. Only allow level 0. 215 */ 216 if (power_level != MPIDR_AFFLVL0) { 217 return PSCI_E_INVALID_PARAMS; 218 } 219 220 /* 221 * From psci view the CPU 0 is always ON, 222 * CPU 1 can be SUSPEND or RUNNING. 223 * Therefore do not manage POWER OFF state and always return HW_ON. 224 */ 225 226 return (int)HW_ON; 227 } 228 229 /******************************************************************************* 230 * Export the platform handlers. The ARM Standard platform layer will take care 231 * of registering the handlers with PSCI. 232 ******************************************************************************/ 233 static const plat_psci_ops_t stm32_psci_ops = { 234 .cpu_standby = stm32_cpu_standby, 235 .pwr_domain_on = stm32_pwr_domain_on, 236 .pwr_domain_off = stm32_pwr_domain_off, 237 .pwr_domain_suspend = stm32_pwr_domain_suspend, 238 .pwr_domain_on_finish = stm32_pwr_domain_on_finish, 239 .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish, 240 .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi, 241 .system_off = stm32_system_off, 242 .system_reset = stm32_system_reset, 243 .validate_power_state = stm32_validate_power_state, 244 .validate_ns_entrypoint = stm32_validate_ns_entrypoint, 245 .get_node_hw_state = stm32_node_hw_state 246 }; 247 248 /******************************************************************************* 249 * Export the platform specific power ops. 250 ******************************************************************************/ 251 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 252 const plat_psci_ops_t **psci_ops) 253 { 254 stm32_sec_entrypoint = sec_entrypoint; 255 *psci_ops = &stm32_psci_ops; 256 257 return 0; 258 } 259