1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <boot_api.h> 10 #include <debug.h> 11 #include <dt-bindings/clock/stm32mp1-clks.h> 12 #include <errno.h> 13 #include <gic_common.h> 14 #include <gicv2.h> 15 #include <mmio.h> 16 #include <platform_def.h> 17 #include <platform.h> 18 #include <psci.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_private.h> 21 #include <stm32mp1_rcc.h> 22 23 static uint32_t stm32_sec_entrypoint; 24 static uint32_t cntfrq_core0; 25 26 #define SEND_SECURE_IT_TO_CORE_1 0x20000U 27 28 /******************************************************************************* 29 * STM32MP1 handler called when a CPU is about to enter standby. 30 * call by core 1 to enter in wfi 31 ******************************************************************************/ 32 static void stm32_cpu_standby(plat_local_state_t cpu_state) 33 { 34 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; 35 36 assert(cpu_state == ARM_LOCAL_STATE_RET); 37 38 /* 39 * Enter standby state 40 * dsb is good practice before using wfi to enter low power states 41 */ 42 dsb(); 43 while (interrupt == GIC_SPURIOUS_INTERRUPT) { 44 wfi(); 45 46 /* Acknoledge IT */ 47 interrupt = gicv2_acknowledge_interrupt(); 48 /* If Interrupt == 1022 it will be acknowledged by non secure */ 49 if ((interrupt != PENDING_G1_INTID) && 50 (interrupt != GIC_SPURIOUS_INTERRUPT)) { 51 gicv2_end_of_interrupt(interrupt); 52 } 53 } 54 } 55 56 /******************************************************************************* 57 * STM32MP1 handler called when a power domain is about to be turned on. The 58 * mpidr determines the CPU to be turned on. 59 * call by core 0 to activate core 1 60 ******************************************************************************/ 61 static int stm32_pwr_domain_on(u_register_t mpidr) 62 { 63 unsigned long current_cpu_mpidr = read_mpidr_el1(); 64 uint32_t tamp_clk_off = 0; 65 uint32_t bkpr_core1_addr = 66 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); 67 uint32_t bkpr_core1_magic = 68 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); 69 70 if (mpidr == current_cpu_mpidr) { 71 return PSCI_E_INVALID_PARAMS; 72 } 73 74 if ((stm32_sec_entrypoint < STM32MP1_SRAM_BASE) || 75 (stm32_sec_entrypoint > (STM32MP1_SRAM_BASE + 76 (STM32MP1_SRAM_SIZE - 1)))) { 77 return PSCI_E_INVALID_ADDRESS; 78 } 79 80 if (!stm32mp1_clk_is_enabled(RTCAPB)) { 81 tamp_clk_off = 1; 82 if (stm32mp1_clk_enable(RTCAPB) != 0) { 83 panic(); 84 } 85 } 86 87 cntfrq_core0 = read_cntfrq_el0(); 88 89 /* Write entrypoint in backup RAM register */ 90 mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint); 91 92 /* Write magic number in backup register */ 93 mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER); 94 95 if (tamp_clk_off != 0U) { 96 if (stm32mp1_clk_disable(RTCAPB) != 0) { 97 panic(); 98 } 99 } 100 101 /* Generate an IT to core 1 */ 102 mmio_write_32(STM32MP1_GICD_BASE + GICD_SGIR, 103 SEND_SECURE_IT_TO_CORE_1 | ARM_IRQ_SEC_SGI_0); 104 105 return PSCI_E_SUCCESS; 106 } 107 108 /******************************************************************************* 109 * STM32MP1 handler called when a power domain is about to be turned off. The 110 * target_state encodes the power state that each level should transition to. 111 ******************************************************************************/ 112 static void stm32_pwr_domain_off(const psci_power_state_t *target_state) 113 { 114 /* Nothing to do */ 115 } 116 117 /******************************************************************************* 118 * STM32MP1 handler called when a power domain is about to be suspended. The 119 * target_state encodes the power state that each level should transition to. 120 ******************************************************************************/ 121 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) 122 { 123 /* Nothing to do, power domain is not disabled */ 124 } 125 126 /******************************************************************************* 127 * STM32MP1 handler called when a power domain has just been powered on after 128 * being turned off earlier. The target_state encodes the low power state that 129 * each level has woken up from. 130 * call by core 1 just after wake up 131 ******************************************************************************/ 132 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) 133 { 134 stm32mp1_gic_pcpu_init(); 135 136 write_cntfrq_el0(cntfrq_core0); 137 } 138 139 /******************************************************************************* 140 * STM32MP1 handler called when a power domain has just been powered on after 141 * having been suspended earlier. The target_state encodes the low power state 142 * that each level has woken up from. 143 ******************************************************************************/ 144 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t 145 *target_state) 146 { 147 /* Nothing to do, power domain is not disabled */ 148 } 149 150 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t 151 *target_state) 152 { 153 ERROR("stm32mpu1 Power Down WFI: operation not handled.\n"); 154 panic(); 155 } 156 157 static void __dead2 stm32_system_off(void) 158 { 159 ERROR("stm32mpu1 System Off: operation not handled.\n"); 160 panic(); 161 } 162 163 static void __dead2 stm32_system_reset(void) 164 { 165 mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST); 166 167 /* Loop in case system reset is not immediately caught */ 168 for ( ; ; ) { 169 ; 170 } 171 } 172 173 static int stm32_validate_power_state(unsigned int power_state, 174 psci_power_state_t *req_state) 175 { 176 int pstate = psci_get_pstate_type(power_state); 177 178 if (pstate != 0) { 179 return PSCI_E_INVALID_PARAMS; 180 } 181 182 if (psci_get_pstate_pwrlvl(power_state)) { 183 return PSCI_E_INVALID_PARAMS; 184 } 185 186 if (psci_get_pstate_id(power_state)) { 187 return PSCI_E_INVALID_PARAMS; 188 } 189 190 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET; 191 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN; 192 193 return PSCI_E_SUCCESS; 194 } 195 196 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint) 197 { 198 /* The non-secure entry point must be in DDR */ 199 if (entrypoint < STM32MP1_DDR_BASE) { 200 return PSCI_E_INVALID_ADDRESS; 201 } 202 203 return PSCI_E_SUCCESS; 204 } 205 206 static int stm32_node_hw_state(u_register_t target_cpu, 207 unsigned int power_level) 208 { 209 /* 210 * The format of 'power_level' is implementation-defined, but 0 must 211 * mean a CPU. Only allow level 0. 212 */ 213 if (power_level != MPIDR_AFFLVL0) { 214 return PSCI_E_INVALID_PARAMS; 215 } 216 217 /* 218 * From psci view the CPU 0 is always ON, 219 * CPU 1 can be SUSPEND or RUNNING. 220 * Therefore do not manage POWER OFF state and always return HW_ON. 221 */ 222 223 return (int)HW_ON; 224 } 225 226 /******************************************************************************* 227 * Export the platform handlers. The ARM Standard platform layer will take care 228 * of registering the handlers with PSCI. 229 ******************************************************************************/ 230 static const plat_psci_ops_t stm32_psci_ops = { 231 .cpu_standby = stm32_cpu_standby, 232 .pwr_domain_on = stm32_pwr_domain_on, 233 .pwr_domain_off = stm32_pwr_domain_off, 234 .pwr_domain_suspend = stm32_pwr_domain_suspend, 235 .pwr_domain_on_finish = stm32_pwr_domain_on_finish, 236 .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish, 237 .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi, 238 .system_off = stm32_system_off, 239 .system_reset = stm32_system_reset, 240 .validate_power_state = stm32_validate_power_state, 241 .validate_ns_entrypoint = stm32_validate_ns_entrypoint, 242 .get_node_hw_state = stm32_node_hw_state 243 }; 244 245 /******************************************************************************* 246 * Export the platform specific power ops. 247 ******************************************************************************/ 248 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 249 const plat_psci_ops_t **psci_ops) 250 { 251 stm32_sec_entrypoint = sec_entrypoint; 252 *psci_ops = &stm32_psci_ops; 253 254 return 0; 255 } 256