1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/st/stm32mp1_clk.h> 17 #include <drivers/st/stm32mp1_rcc.h> 18 #include <dt-bindings/clock/stm32mp1-clks.h> 19 #include <lib/mmio.h> 20 #include <lib/psci/psci.h> 21 #include <plat/common/platform.h> 22 23 static uintptr_t stm32_sec_entrypoint; 24 static uint32_t cntfrq_core0; 25 26 /******************************************************************************* 27 * STM32MP1 handler called when a CPU is about to enter standby. 28 * call by core 1 to enter in wfi 29 ******************************************************************************/ 30 static void stm32_cpu_standby(plat_local_state_t cpu_state) 31 { 32 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; 33 34 assert(cpu_state == ARM_LOCAL_STATE_RET); 35 36 /* 37 * Enter standby state 38 * dsb is good practice before using wfi to enter low power states 39 */ 40 isb(); 41 dsb(); 42 while (interrupt == GIC_SPURIOUS_INTERRUPT) { 43 wfi(); 44 45 /* Acknoledge IT */ 46 interrupt = gicv2_acknowledge_interrupt(); 47 /* If Interrupt == 1022 it will be acknowledged by non secure */ 48 if ((interrupt != PENDING_G1_INTID) && 49 (interrupt != GIC_SPURIOUS_INTERRUPT)) { 50 gicv2_end_of_interrupt(interrupt); 51 } 52 } 53 } 54 55 /******************************************************************************* 56 * STM32MP1 handler called when a power domain is about to be turned on. The 57 * mpidr determines the CPU to be turned on. 58 * call by core 0 to activate core 1 59 ******************************************************************************/ 60 static int stm32_pwr_domain_on(u_register_t mpidr) 61 { 62 unsigned long current_cpu_mpidr = read_mpidr_el1(); 63 uint32_t tamp_clk_off = 0; 64 uint32_t bkpr_core1_addr = 65 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); 66 uint32_t bkpr_core1_magic = 67 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); 68 69 if (mpidr == current_cpu_mpidr) { 70 return PSCI_E_INVALID_PARAMS; 71 } 72 73 if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) || 74 (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE + 75 (STM32MP_SYSRAM_SIZE - 1)))) { 76 return PSCI_E_INVALID_ADDRESS; 77 } 78 79 if (!stm32mp_clk_is_enabled(RTCAPB)) { 80 tamp_clk_off = 1; 81 if (stm32mp_clk_enable(RTCAPB) != 0) { 82 panic(); 83 } 84 } 85 86 cntfrq_core0 = read_cntfrq_el0(); 87 88 /* Write entrypoint in backup RAM register */ 89 mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint); 90 91 /* Write magic number in backup register */ 92 mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER); 93 94 if (tamp_clk_off != 0U) { 95 if (stm32mp_clk_disable(RTCAPB) != 0) { 96 panic(); 97 } 98 } 99 100 /* Generate an IT to core 1 */ 101 gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU); 102 103 return PSCI_E_SUCCESS; 104 } 105 106 /******************************************************************************* 107 * STM32MP1 handler called when a power domain is about to be turned off. The 108 * target_state encodes the power state that each level should transition to. 109 ******************************************************************************/ 110 static void stm32_pwr_domain_off(const psci_power_state_t *target_state) 111 { 112 /* Nothing to do */ 113 } 114 115 /******************************************************************************* 116 * STM32MP1 handler called when a power domain is about to be suspended. The 117 * target_state encodes the power state that each level should transition to. 118 ******************************************************************************/ 119 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) 120 { 121 /* Nothing to do, power domain is not disabled */ 122 } 123 124 /******************************************************************************* 125 * STM32MP1 handler called when a power domain has just been powered on after 126 * being turned off earlier. The target_state encodes the low power state that 127 * each level has woken up from. 128 * call by core 1 just after wake up 129 ******************************************************************************/ 130 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) 131 { 132 stm32mp1_gic_pcpu_init(); 133 134 write_cntfrq_el0(cntfrq_core0); 135 } 136 137 /******************************************************************************* 138 * STM32MP1 handler called when a power domain has just been powered on after 139 * having been suspended earlier. The target_state encodes the low power state 140 * that each level has woken up from. 141 ******************************************************************************/ 142 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t 143 *target_state) 144 { 145 /* Nothing to do, power domain is not disabled */ 146 } 147 148 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t 149 *target_state) 150 { 151 ERROR("stm32mpu1 Power Down WFI: operation not handled.\n"); 152 panic(); 153 } 154 155 static void __dead2 stm32_system_off(void) 156 { 157 ERROR("stm32mpu1 System Off: operation not handled.\n"); 158 panic(); 159 } 160 161 static void __dead2 stm32_system_reset(void) 162 { 163 mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST); 164 165 /* Loop in case system reset is not immediately caught */ 166 for ( ; ; ) { 167 ; 168 } 169 } 170 171 static int stm32_validate_power_state(unsigned int power_state, 172 psci_power_state_t *req_state) 173 { 174 int pstate = psci_get_pstate_type(power_state); 175 176 if (pstate != 0) { 177 return PSCI_E_INVALID_PARAMS; 178 } 179 180 if (psci_get_pstate_pwrlvl(power_state)) { 181 return PSCI_E_INVALID_PARAMS; 182 } 183 184 if (psci_get_pstate_id(power_state)) { 185 return PSCI_E_INVALID_PARAMS; 186 } 187 188 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET; 189 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN; 190 191 return PSCI_E_SUCCESS; 192 } 193 194 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint) 195 { 196 /* The non-secure entry point must be in DDR */ 197 if (entrypoint < STM32MP_DDR_BASE) { 198 return PSCI_E_INVALID_ADDRESS; 199 } 200 201 return PSCI_E_SUCCESS; 202 } 203 204 static int stm32_node_hw_state(u_register_t target_cpu, 205 unsigned int power_level) 206 { 207 /* 208 * The format of 'power_level' is implementation-defined, but 0 must 209 * mean a CPU. Only allow level 0. 210 */ 211 if (power_level != MPIDR_AFFLVL0) { 212 return PSCI_E_INVALID_PARAMS; 213 } 214 215 /* 216 * From psci view the CPU 0 is always ON, 217 * CPU 1 can be SUSPEND or RUNNING. 218 * Therefore do not manage POWER OFF state and always return HW_ON. 219 */ 220 221 return (int)HW_ON; 222 } 223 224 /******************************************************************************* 225 * Export the platform handlers. The ARM Standard platform layer will take care 226 * of registering the handlers with PSCI. 227 ******************************************************************************/ 228 static const plat_psci_ops_t stm32_psci_ops = { 229 .cpu_standby = stm32_cpu_standby, 230 .pwr_domain_on = stm32_pwr_domain_on, 231 .pwr_domain_off = stm32_pwr_domain_off, 232 .pwr_domain_suspend = stm32_pwr_domain_suspend, 233 .pwr_domain_on_finish = stm32_pwr_domain_on_finish, 234 .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish, 235 .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi, 236 .system_off = stm32_system_off, 237 .system_reset = stm32_system_reset, 238 .validate_power_state = stm32_validate_power_state, 239 .validate_ns_entrypoint = stm32_validate_ns_entrypoint, 240 .get_node_hw_state = stm32_node_hw_state 241 }; 242 243 /******************************************************************************* 244 * Export the platform specific power ops. 245 ******************************************************************************/ 246 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 247 const plat_psci_ops_t **psci_ops) 248 { 249 stm32_sec_entrypoint = sec_entrypoint; 250 *psci_ops = &stm32_psci_ops; 251 252 return 0; 253 } 254