1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <common/bl_common.h> 12#include <drivers/st/stm32_gpio.h> 13 14#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1) 15#define GPIO_TX_ALT_SHIFT ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2) 16 17 .globl platform_mem_init 18 .globl plat_report_exception 19 .globl plat_get_my_entrypoint 20 .globl plat_secondary_cold_boot_setup 21 .globl plat_reset_handler 22 .globl plat_is_my_cpu_primary 23 .globl plat_my_core_pos 24 .globl plat_crash_console_init 25 .globl plat_crash_console_flush 26 .globl plat_crash_console_putc 27 .globl plat_panic_handler 28 29func platform_mem_init 30 /* Nothing to do, don't need to init SYSRAM */ 31 bx lr 32endfunc platform_mem_init 33 34func plat_report_exception 35 bx lr 36endfunc plat_report_exception 37 38func plat_reset_handler 39 bx lr 40endfunc plat_reset_handler 41 42 /* ------------------------------------------------------------------ 43 * unsigned long plat_get_my_entrypoint (void); 44 * 45 * Main job of this routine is to distinguish between a cold and warm 46 * boot. 47 * 48 * Currently supports only cold boot 49 * ------------------------------------------------------------------ 50 */ 51func plat_get_my_entrypoint 52 mov r0, #0 53 bx lr 54endfunc plat_get_my_entrypoint 55 56 /* --------------------------------------------- 57 * void plat_secondary_cold_boot_setup (void); 58 * 59 * Cold-booting secondary CPUs is not supported. 60 * --------------------------------------------- 61 */ 62func plat_secondary_cold_boot_setup 63 b . 64endfunc plat_secondary_cold_boot_setup 65 66 /* ----------------------------------------------------- 67 * unsigned int plat_is_my_cpu_primary (void); 68 * 69 * Find out whether the current cpu is the primary cpu. 70 * ----------------------------------------------------- 71 */ 72func plat_is_my_cpu_primary 73 ldcopr r0, MPIDR 74 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 75 and r0, r1 76 cmp r0, #STM32MP_PRIMARY_CPU 77 moveq r0, #1 78 movne r0, #0 79 bx lr 80endfunc plat_is_my_cpu_primary 81 82 /* ------------------------------------------- 83 * int plat_stm32mp1_get_core_pos(int mpidr); 84 * 85 * Return CorePos = (ClusterId * 4) + CoreId 86 * ------------------------------------------- 87 */ 88func plat_stm32mp1_get_core_pos 89 and r1, r0, #MPIDR_CPU_MASK 90 and r0, r0, #MPIDR_CLUSTER_MASK 91 add r0, r1, r0, LSR #6 92 bx lr 93endfunc plat_stm32mp1_get_core_pos 94 95 /* ------------------------------------ 96 * unsigned int plat_my_core_pos(void) 97 * ------------------------------------ 98 */ 99func plat_my_core_pos 100 ldcopr r0, MPIDR 101 b plat_stm32mp1_get_core_pos 102endfunc plat_my_core_pos 103 104 /* --------------------------------------------- 105 * int plat_crash_console_init(void) 106 * 107 * Initialize the crash console without a C Runtime stack. 108 * --------------------------------------------- 109 */ 110func plat_crash_console_init 111 /* Enable GPIOs for UART TX */ 112 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG) 113 ldr r2, [r1] 114 /* Configure GPIO */ 115 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN 116 str r2, [r1] 117 ldr r1, =DEBUG_UART_TX_GPIO_BANK_ADDRESS 118 /* Set GPIO mode alternate */ 119 ldr r2, [r1, #GPIO_MODE_OFFSET] 120 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) 121 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) 122 str r2, [r1, #GPIO_MODE_OFFSET] 123 /* Set GPIO speed low */ 124 ldr r2, [r1, #GPIO_SPEED_OFFSET] 125 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) 126 str r2, [r1, #GPIO_SPEED_OFFSET] 127 /* Set no-pull */ 128 ldr r2, [r1, #GPIO_PUPD_OFFSET] 129 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) 130 str r2, [r1, #GPIO_PUPD_OFFSET] 131 /* Set alternate */ 132 ldr r2, [r1, #GPIO_AFRH_OFFSET] 133 bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT) 134 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << GPIO_TX_ALT_SHIFT) 135 str r2, [r1, #GPIO_AFRH_OFFSET] 136 /* Enable UART clock, with its source */ 137 ldr r1, =(RCC_BASE + DEBUG_UART_TX_CLKSRC_REG) 138 mov r2, #DEBUG_UART_TX_CLKSRC 139 str r2, [r1] 140 ldr r1, =(RCC_BASE + DEBUG_UART_TX_EN_REG) 141 ldr r2, [r1] 142 orr r2, r2, #DEBUG_UART_TX_EN 143 str r2, [r1] 144 145 ldr r0, =STM32MP_DEBUG_USART_BASE 146 ldr r1, =STM32MP_DEBUG_USART_CLK_FRQ 147 ldr r2, =STM32MP_UART_BAUDRATE 148 b console_stm32_core_init 149endfunc plat_crash_console_init 150 151 /* --------------------------------------------- 152 * int plat_crash_console_flush(void) 153 * 154 * Flush the crash console without a C Runtime stack. 155 * --------------------------------------------- 156 */ 157func plat_crash_console_flush 158 ldr r1, =STM32MP_DEBUG_USART_BASE 159 b console_stm32_core_flush 160endfunc plat_crash_console_flush 161 162 /* --------------------------------------------- 163 * int plat_crash_console_putc(int c) 164 * 165 * Print a character on the crash console without a C Runtime stack. 166 * Clobber list : r1 - r3 167 * 168 * In case of bootloading through uart, we keep console crash as this. 169 * Characters could be sent to the programmer, but will be ignored. 170 * No specific code in that case. 171 * --------------------------------------------- 172 */ 173func plat_crash_console_putc 174 ldr r1, =STM32MP_DEBUG_USART_BASE 175 b console_stm32_core_putc 176endfunc plat_crash_console_putc 177