1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <common/bl_common.h> 12#include <drivers/st/stm32_gpio.h> 13#include <drivers/st/stm32mp1_rcc.h> 14 15#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1) 16#define GPIO_TX_ALT_SHIFT ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2) 17 18 .globl platform_mem_init 19 .globl plat_report_exception 20 .globl plat_get_my_entrypoint 21 .globl plat_secondary_cold_boot_setup 22 .globl plat_reset_handler 23 .globl plat_is_my_cpu_primary 24 .globl plat_my_core_pos 25 .globl plat_crash_console_init 26 .globl plat_crash_console_flush 27 .globl plat_crash_console_putc 28 .globl plat_panic_handler 29 30func platform_mem_init 31 /* Nothing to do, don't need to init SYSRAM */ 32 bx lr 33endfunc platform_mem_init 34 35func plat_report_exception 36 bx lr 37endfunc plat_report_exception 38 39func plat_reset_handler 40 bx lr 41endfunc plat_reset_handler 42 43 /* ------------------------------------------------------------------ 44 * unsigned long plat_get_my_entrypoint (void); 45 * 46 * Main job of this routine is to distinguish between a cold and warm 47 * boot. 48 * 49 * Currently supports only cold boot 50 * ------------------------------------------------------------------ 51 */ 52func plat_get_my_entrypoint 53 mov r0, #0 54 bx lr 55endfunc plat_get_my_entrypoint 56 57 /* --------------------------------------------- 58 * void plat_secondary_cold_boot_setup (void); 59 * 60 * Cold-booting secondary CPUs is not supported. 61 * --------------------------------------------- 62 */ 63func plat_secondary_cold_boot_setup 64 b . 65endfunc plat_secondary_cold_boot_setup 66 67 /* ----------------------------------------------------- 68 * unsigned int plat_is_my_cpu_primary (void); 69 * 70 * Find out whether the current cpu is the primary cpu. 71 * ----------------------------------------------------- 72 */ 73func plat_is_my_cpu_primary 74 ldcopr r0, MPIDR 75 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 76 and r0, r1 77 cmp r0, #STM32MP1_PRIMARY_CPU 78 moveq r0, #1 79 movne r0, #0 80 bx lr 81endfunc plat_is_my_cpu_primary 82 83 /* ------------------------------------------- 84 * int plat_stm32mp1_get_core_pos(int mpidr); 85 * 86 * Return CorePos = (ClusterId * 4) + CoreId 87 * ------------------------------------------- 88 */ 89func plat_stm32mp1_get_core_pos 90 and r1, r0, #MPIDR_CPU_MASK 91 and r0, r0, #MPIDR_CLUSTER_MASK 92 add r0, r1, r0, LSR #6 93 bx lr 94endfunc plat_stm32mp1_get_core_pos 95 96 /* ------------------------------------ 97 * unsigned int plat_my_core_pos(void) 98 * ------------------------------------ 99 */ 100func plat_my_core_pos 101 ldcopr r0, MPIDR 102 b plat_stm32mp1_get_core_pos 103endfunc plat_my_core_pos 104 105 /* --------------------------------------------- 106 * int plat_crash_console_init(void) 107 * 108 * Initialize the crash console without a C Runtime stack. 109 * --------------------------------------------- 110 */ 111func plat_crash_console_init 112 /* Enable GPIOs for UART TX */ 113 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG) 114 ldr r2, [r1] 115 /* Configure GPIO */ 116 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN 117 str r2, [r1] 118 ldr r1, =DEBUG_UART_TX_GPIO_BANK_ADDRESS 119 /* Set GPIO mode alternate */ 120 ldr r2, [r1, #GPIO_MODE_OFFSET] 121 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) 122 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) 123 str r2, [r1, #GPIO_MODE_OFFSET] 124 /* Set GPIO speed low */ 125 ldr r2, [r1, #GPIO_SPEED_OFFSET] 126 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) 127 str r2, [r1, #GPIO_SPEED_OFFSET] 128 /* Set no-pull */ 129 ldr r2, [r1, #GPIO_PUPD_OFFSET] 130 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) 131 str r2, [r1, #GPIO_PUPD_OFFSET] 132 /* Set alternate */ 133 ldr r2, [r1, #GPIO_AFRH_OFFSET] 134 bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT) 135 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << GPIO_TX_ALT_SHIFT) 136 str r2, [r1, #GPIO_AFRH_OFFSET] 137 /* Enable UART clock, with its source */ 138 ldr r1, =(RCC_BASE + DEBUG_UART_TX_CLKSRC_REG) 139 mov r2, #DEBUG_UART_TX_CLKSRC 140 str r2, [r1] 141 ldr r1, =(RCC_BASE + DEBUG_UART_TX_EN_REG) 142 ldr r2, [r1] 143 orr r2, r2, #DEBUG_UART_TX_EN 144 str r2, [r1] 145 146 ldr r0, =STM32MP1_DEBUG_USART_BASE 147 ldr r1, =STM32MP1_DEBUG_USART_CLK_FRQ 148 ldr r2, =STM32MP1_UART_BAUDRATE 149 b console_stm32_core_init 150endfunc plat_crash_console_init 151 152 /* --------------------------------------------- 153 * int plat_crash_console_flush(void) 154 * 155 * Flush the crash console without a C Runtime stack. 156 * --------------------------------------------- 157 */ 158func plat_crash_console_flush 159 ldr r1, =STM32MP1_DEBUG_USART_BASE 160 b console_stm32_core_flush 161endfunc plat_crash_console_flush 162 163 /* --------------------------------------------- 164 * int plat_crash_console_putc(int c) 165 * 166 * Print a character on the crash console without a C Runtime stack. 167 * Clobber list : r1 - r3 168 * 169 * In case of bootloading through uart, we keep console crash as this. 170 * Characters could be sent to the programmer, but will be ignored. 171 * No specific code in that case. 172 * --------------------------------------------- 173 */ 174func plat_crash_console_putc 175 ldr r1, =STM32MP1_DEBUG_USART_BASE 176 b console_stm32_core_putc 177endfunc plat_crash_console_putc 178