1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <common/bl_common.h> 12#include <drivers/st/stm32_gpio.h> 13#include <drivers/st/stm32mp1_rcc.h> 14 15#define GPIO_BANK_G_ADDRESS 0x50008000 16#define GPIO_TX_PORT 11 17#define GPIO_TX_SHIFT (GPIO_TX_PORT << 1) 18#define GPIO_TX_ALT_SHIFT ((GPIO_TX_PORT - GPIO_ALT_LOWER_LIMIT) << 2) 19#define STM32MP1_HSI_CLK 64000000 20 21 .globl platform_mem_init 22 .globl plat_report_exception 23 .globl plat_get_my_entrypoint 24 .globl plat_secondary_cold_boot_setup 25 .globl plat_reset_handler 26 .globl plat_is_my_cpu_primary 27 .globl plat_my_core_pos 28 .globl plat_crash_console_init 29 .globl plat_crash_console_flush 30 .globl plat_crash_console_putc 31 .globl plat_panic_handler 32 33func platform_mem_init 34 /* Nothing to do, don't need to init SYSRAM */ 35 bx lr 36endfunc platform_mem_init 37 38func plat_report_exception 39 bx lr 40endfunc plat_report_exception 41 42func plat_reset_handler 43 bx lr 44endfunc plat_reset_handler 45 46 /* ------------------------------------------------------------------ 47 * unsigned long plat_get_my_entrypoint (void); 48 * 49 * Main job of this routine is to distinguish between a cold and warm 50 * boot. 51 * 52 * Currently supports only cold boot 53 * ------------------------------------------------------------------ 54 */ 55func plat_get_my_entrypoint 56 mov r0, #0 57 bx lr 58endfunc plat_get_my_entrypoint 59 60 /* --------------------------------------------- 61 * void plat_secondary_cold_boot_setup (void); 62 * 63 * Cold-booting secondary CPUs is not supported. 64 * --------------------------------------------- 65 */ 66func plat_secondary_cold_boot_setup 67 b . 68endfunc plat_secondary_cold_boot_setup 69 70 /* ----------------------------------------------------- 71 * unsigned int plat_is_my_cpu_primary (void); 72 * 73 * Find out whether the current cpu is the primary cpu. 74 * ----------------------------------------------------- 75 */ 76func plat_is_my_cpu_primary 77 ldcopr r0, MPIDR 78 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 79 and r0, r1 80 cmp r0, #STM32MP1_PRIMARY_CPU 81 moveq r0, #1 82 movne r0, #0 83 bx lr 84endfunc plat_is_my_cpu_primary 85 86 /* ------------------------------------------- 87 * int plat_stm32mp1_get_core_pos(int mpidr); 88 * 89 * Return CorePos = (ClusterId * 4) + CoreId 90 * ------------------------------------------- 91 */ 92func plat_stm32mp1_get_core_pos 93 and r1, r0, #MPIDR_CPU_MASK 94 and r0, r0, #MPIDR_CLUSTER_MASK 95 add r0, r1, r0, LSR #6 96 bx lr 97endfunc plat_stm32mp1_get_core_pos 98 99 /* ------------------------------------ 100 * unsigned int plat_my_core_pos(void) 101 * ------------------------------------ 102 */ 103func plat_my_core_pos 104 ldcopr r0, MPIDR 105 b plat_stm32mp1_get_core_pos 106endfunc plat_my_core_pos 107 108 /* --------------------------------------------- 109 * int plat_crash_console_init(void) 110 * 111 * Initialize the crash console without a C Runtime stack. 112 * --------------------------------------------- 113 */ 114func plat_crash_console_init 115 /* Enable GPIOs for UART4 TX */ 116 ldr r1, =(RCC_BASE + RCC_MP_AHB4ENSETR) 117 ldr r2, [r1] 118 /* Configure GPIO G11 */ 119 orr r2, r2, #RCC_MP_AHB4ENSETR_GPIOGEN 120 str r2, [r1] 121 ldr r1, =GPIO_BANK_G_ADDRESS 122 /* Set GPIO mode alternate */ 123 ldr r2, [r1, #GPIO_MODE_OFFSET] 124 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) 125 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) 126 str r2, [r1, #GPIO_MODE_OFFSET] 127 /* Set GPIO speed low */ 128 ldr r2, [r1, #GPIO_SPEED_OFFSET] 129 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) 130 str r2, [r1, #GPIO_SPEED_OFFSET] 131 /* Set no-pull */ 132 ldr r2, [r1, #GPIO_PUPD_OFFSET] 133 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) 134 str r2, [r1, #GPIO_PUPD_OFFSET] 135 /* Set alternate AF6 */ 136 ldr r2, [r1, #GPIO_AFRH_OFFSET] 137 bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT) 138 orr r2, r2, #(GPIO_ALTERNATE_6 << GPIO_TX_ALT_SHIFT) 139 str r2, [r1, #GPIO_AFRH_OFFSET] 140 141 /* Enable UART clock, with HSI source */ 142 ldr r1, =(RCC_BASE + RCC_UART24CKSELR) 143 mov r2, #RCC_UART24CKSELR_HSI 144 str r2, [r1] 145 ldr r1, =(RCC_BASE + RCC_MP_APB1ENSETR) 146 ldr r2, [r1] 147 orr r2, r2, #RCC_MP_APB1ENSETR_UART4EN 148 str r2, [r1] 149 150 ldr r0, =STM32MP1_DEBUG_USART_BASE 151 ldr r1, =STM32MP1_HSI_CLK 152 ldr r2, =STM32MP1_UART_BAUDRATE 153 b console_stm32_core_init 154endfunc plat_crash_console_init 155 156 /* --------------------------------------------- 157 * int plat_crash_console_flush(void) 158 * 159 * Flush the crash console without a C Runtime stack. 160 * --------------------------------------------- 161 */ 162func plat_crash_console_flush 163 ldr r1, =STM32MP1_DEBUG_USART_BASE 164 b console_stm32_core_flush 165endfunc plat_crash_console_flush 166 167 /* --------------------------------------------- 168 * int plat_crash_console_putc(int c) 169 * 170 * Print a character on the crash console without a C Runtime stack. 171 * Clobber list : r1 - r3 172 * 173 * In case of bootloading through uart, we keep console crash as this. 174 * Characters could be sent to the programmer, but will be ignored. 175 * No specific code in that case. 176 * --------------------------------------------- 177 */ 178func plat_crash_console_putc 179 ldr r1, =STM32MP1_DEBUG_USART_BASE 180 b console_stm32_core_putc 181endfunc plat_crash_console_putc 182